Koichiro ISHIBASHI
| Emeritus Professor etc. | Emeritus Professor |
Researcher Information
Research Keyword
Field Of Study
Career
- 01 Apr. 2004 - 31 Mar. 2011
Renesas Electronics Corp., 技術開発本部 設計技術統括部, 基盤IP開発部長 - 01 Oct. 2001 - 31 Mar. 2004
Semiconductor Technology Academic Research Center (STARC), 設計技術開発部 低電力技術開発室, Low Power Technology Development Dept. - 01 Apr. 1985 - 30 Sep. 2001
Central Research Laboratory, Hitachi Ltd., ULSI研究センター, 主任研究員 631研究ユニット ユニットリーダー
Educational Background
Member History
- 2016
Steering Committee member, FDSE(International Conference on Future Data and Security Engineering), Society - 2016
Steering Committee member, FDSE(International Conference on Future Data and Security Engineering), Society - 2016
Steering Committee member, ACOMP(International Conference on Advanced Computing and Applications), Society - 2016
Steering Committee member, ACOMP(International Conference on Advanced Computing and Applications), Society - 01 Aug. 2013
ACOMP Program Committee, Others - Apr. 2011
集積回路研究会 基盤ＩＰＣチェア, 電気情報通信学会, Society - Jan. 2005
Fellow 2005-, IEEE, Society - Jan. 2005
Fellow 2005-, IEEE, Society
Research Activity Information
Award
- Jun. 2018
2018 Thailand-Japan MicroWave (TJMW2018)
2018 Thailand-Japan MicroWave (TJMW2018) Young researcher encouragement award
International society - Dec. 2013
2013 Thailand-Japan MicroWave (TJMW2013)
2013 Thailand-Japan MicroWave (TJMW2013) Young researcher encouragement award - 2010
平成２２年度 関東地方発明表彰 発明奨励賞 - Feb. 2005
IEEE
ＵＳＡ
IEEE Fellow Award
United States - Feb. 2003
ISSCC 2003 Program Committee
USA
Technical-Paper Presentations at ISSCC 1964-2003 on the occasion of the ISSCC 50th anniversary
United States - 2001
マイコンの超低電力化回路技術
2001年度武田研究奨励賞 - 1999
R&D 100 1999 (selected by R & D 100 magazine) - Mar. 1988
西８号館 空調用熱源機器（暖房）運転管理方法
手島工業教育資金団 研究論文賞
Paper
- Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications
Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Ronaldo Serrano; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham
IEEE Transactions on Circuits and Systems II, 69, 5, 22 Mar. 2022, Peer-reviwed
International conference proceedings, English - Small-Scale Depthwise Separable Convolutional Neural Networks for Bacteria Classification
Duc-Tho Mai; Koichiro Ishibashi
MDPI Journal of Electronics 2021, 10(23)3005, Dec. 2021, Peer-reviwed
Scientific journal, English - Bacteria Shape Classification using Small-Scale Depthwise Separable CNNs
Duc-Tho Mai; Koichiro Ishibashi
1, 01 Nov. 2021, Peer-reviwed
International conference proceedings, English - Infectious Disease Screening system using Medical Radar and Data Quality Assessment by Efficient Neural Network Hardware
Koki Kumagai; Duc-Tho Mai; Koichiro Ishibashi
1, 22 Oct. 2021, Peer-reviwed
International conference proceedings, English - A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications
Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Khai-Duy Nguyen; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham
1, 06 Oct. 2021, Peer-reviwed
International conference proceedings, English - A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications
Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham
IEEE Transactions on Circuits and Systems II, vol. 68, 9, 3182-3186, Sep. 2021, Peer-reviwed
Scientific journal, English - Bacteria Shape Recognition with the Kotobuki's model
Duc-Tho Mai; Koichiro Ishibashi
生体医工学会, 59, 859, 17 Jun. 2021, Peer-reviwed
Symposium, English - High Accuracy Heartbeat Detection from CW-Doppler Radar Using Singular Value Decomposition and Matched Filter
Yuki Iwata; Han Trong Thanh; Guanghao Sun; Koichiro Ishibashi
MDPI Journal of Sensors 2021, 21, 3588, May 2021, Peer-reviwed
Scientific journal, English - Analysis of Drain Current Enhancement in "PN-Body Tied SOI-FET" -Bulk vs Surface Conduction Mode and Low Vds Saturation Effect-
Hiroki Itoh; Jiro Ida; Takayuki Mori; Koichiro Ishibashi
2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), IEEE, 19 Apr. 2021
International conference proceedings - Transfer Characteristics of CMOS Inverter using Steep SS PN-Body Tied SOI-FET
Shota Ishiguro; Jiro Ida; Takayuki Mori; Koichiro Ishibashi
1, 1, 19 Apr. 2021, Peer-reviwed
International conference proceedings, English - A Concurrent Triple-band RF Energy Harvesting Circuit for IoT Sensor Networks
Luong Duy Manh; Phan Thi Bich; Nguyen Thuy Linh; Nguyen Huy Hoang; Tran Xuan Nam; Koichiro Ishibashi
IEIE Transactions on Smart Processing and Computing, vol.10, no. 2, 1-9, Apr. 2021, Peer-reviwed
Scientific journal, English - A Concurrent Triple-band RF Energy Harvesting Circuit for IoT Sensor Networks
Luong Duy Manh; Phan Thi Bich; Nguyen Thuy Linh; Nguyen Huy Hoang; Tran Xuan Nam; Koichiro Ishibashi
IEIE Transactions on Smart Processing and Computing, 10, 2, 01 Apr. 2021, Peer-reviwed
Scientific journal, English - Effects of Modulated Waveform on RF Energy Harvesting
Linh Thuy Nguyen; Luong Duy Manh; Koichiro Ishibashi
Proceedings of ICGHIT 2021, 1, 13 Jan. 2021, Peer-reviwed
International conference proceedings, English - Effect of Modulated Waveform on RF Energy Harvesting
Nguyen Thuy Linh; Luong Duy Manh; Koichiro Ishibashi; “Effect of; Modulated; Waveform on; RF Energy Harvesting
1, 1, 13 Jan. 2021, Peer-reviwed
International conference proceedings, English - Machine Learning based Classification Model for Screening of Infected Patients Using Vital Signs
Thanh Han Trong; Yen Pham Huong; Lam Nguyen; Dang Son; Yuki Iwata; Tuan Do Trong; Koichiro Ishibashi; Guanghao Sun
Informatics in Medicine Unlocked, vol. 24 100592, 2021, Peer-reviwed
Scientific journal, English - Short time cardio-vascular pulses estimation for dengue fever screening via continuous-wave Doppler radar using empirical mode decomposition and continuous wavelet transform
Nguyen Dinh Chinh; Luu Manh Ha; GuanghaoSun; Le Quoc Anh; Pham Viet Huong; Tran Anh Vu; Tran Trong Hieu; Tran Duc Tan; Nguyen Vu Trung; Koichiro Ishibashi; Nguyen Linh Trung
Elsevier, Elsevier, Vol.65, 102361, 2021, Peer-reviwed
Scientific journal, English - 7.6 uW Ambient Energy Harvesting Rectenna from LTE Mobile phone Signal for IoT Applications
Linh Nguyen; Yasuo Sato; Koichiro Ishibashi
International Conference on Advanced Technologies for Communications (ATC 2020), 1, 08 Oct. 2020, Peer-reviwed
International conference proceedings, English - Energy Harvesting from Environment RF for IoT Applications
Koichiro Ishibashi
International Conference on Advanced Technologies for Communications (ATC 2020), 1, 08 Oct. 2020, Peer-reviwed, Invited
International conference proceedings, English - 7.6 uW Ambient Energy Harvesting Rectenna from LTE Mobile phone Signal for IoT Applications
Linh Nguyen; Yasuo Sato; Koichiro Ishibashi
1, 1, 01 Oct. 2020, Peer-reviwed
International conference proceedings, English - RF Energy Harvesting using Cross-couple Rectifier and DTMOS on SOTB with Phase Effect of Paired RF Inputs
Thuy-Linh Nguyen; Shiho Takahashi; Van-Trung Nguyen; Yasuo Sato; Koichiro Ishibashi
ECTI Transactions on Electrical Engineering, Vol.18, No.2, 170-178, 01 Aug. 2020, Peer-reviwed
International conference proceedings, English - Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis
Yuki IWATA; Koichiro ISHIBASHI; Guanghao SUN; Manh Ha LUU; Trong Thanh HAN; Linh Trung NGUYEN; Trong Tuan DO
Conference Paper | Publisher: IEEE, 1, 20 Jul. 2020, Peer-reviwed
International conference proceedings, English - Visualization of epidemiological map using an Internet of Things infectious disease surveillance platform
Guanghao Sun; Nguyen Vu Trung; Le Thi Hoi; Pham Thanh Hiep; Koichiro Ishibashi; Takemi Matsui
Critical Care, Vol.24, Article number 400, 1-1, 01 Jul. 2020, Peer-reviwed
Scientific journal, English - Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis
Yuki IWATA; Koichiro ISHIBASHI; Guanghao SUN; Manh Ha LUU; Trong Thanh HAN; Linh Trung NGUYEN; Trong Tuan DO
1, 1, 01 Jul. 2020, Peer-reviwed
International conference proceedings, English - Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis
Yuki IWATA; Koichiro ISHIBASHI; Guanghao SUN; Manh Ha LUU; Trong Thanh HAN; Linh Trung NGUYEN; Trong Tuan DO
2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), 1, 20 Jun. 2020, Peer-reviwed
International conference proceedings, English - CR-SSAによる呼吸及び体動下での非接触な心拍検出
岩田 勇樹; 石橋 孝一郎; 孫 光鎬; ルー マンハ; ハン チョンタイン; グエン リンチュン; ド チョントゥアン
ジャーナル フリー, Annual58, Abstract, 455, 25 May 2020, Peer-reviwed
International conference proceedings, Japanese - A Novel Circuit Combining a Dual-Band Antenna with a RF Diplexer for Concurrent Dual-Band RF Energy Harvesting Applications
Luong Duy Manh; Phan Thi Bich; Truong Anh Dung; Koichiro Ishibashi
1, 1-1, 01 Feb. 2020, Peer-reviwed
International conference proceedings, English - Machine Learning Algorithms for Dengue Fever Patient Classification,
Han Trong Thanh; Pham Huong Yen; Koichiro Ishibashi; Guanghao Sun; Tuan Do Trong
1, 1, 14 Jan. 2020, Peer-reviwed
International conference proceedings, English - Visualisation of epidemiological map using an Internet of Things infectious disease surveillance platform
Guanghao Sun; Nguyen Vu Trung; Le Thi Hoi; Pham Thanh Hiep; Koichiro Ishibashi; Takemi Matsui
Critical Care, 24, 400, 2020, Peer-reviwed
Scientific journal, English - A Novel Circuit Combining a Dual-Band Antenna with a RF Diplexer for Concurrent Dual-Band RF Energy Harvesting Applications, Luong Duy Manh ; Phan Thi Bich
Luong Duy Manh; Phan Thi Bich; Truong Anh Dung; Koichiro Ishibashi
2020 International Conference on Green and Human Information Technology, 1, 2020, Peer-reviwed
International conference proceedings, English - Short Time Cardio-vascular Pulses Estimation for Dengue Fever Screening via Continuous-Wave Doppler Radar using Empirical Mode Decomposition and Continuous Wavelet Transform
Ha Luu; Chinh D Nguyen, MSc; Guanghao Sun; Assis. Prof. Ph.D; Anh Q Le, BCs; Huong V Pham, Ph.D; Vu A Tran, Ph.D; Hieu T Tran, Ph.D; Tan D Tran; Assoc.Prof. Ph.D; Trung V Nguyen; Assoc.Prof. Ph.D; Koichiro Ishibashi; Prof. Ph.D; Trung L Nguyen; Assoc.Prof. Ph.D
Biomedical Signal Processing and Control 2020, 1, 2020, Peer-reviwed
International conference proceedings, English - A Novel Circuit Combining a Dual-Band Antenna with a RF Diplexer for Concurrent Dual-Band RF Energy Harvesting Applications
Luong Duy Manh; Phan Thi Bich; Truong Anh Dung; Koichiro Ishibashi
2020 International Conference on Green and Human Information Technology (ICGHIT), 1, 2020, Peer-reviwed
International conference proceedings, English - Super steep SS "PN-Body tied SOI-FET" with 65 nm thin Box FD-SOI
Keita Daimatsu; Jiro Ida; Takuya Yamada; Takayuki Mori; Koichiro Ishibashi
2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) PROCEEDINGS, p117-118, 2019, November 13-15, 2019 Sofitel Chengdu Taihe, Chengdu, Sichuan, China, IEEE, Nov. 2019, Peer-reviwed
International conference proceedings, English - Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS “PN Body-Tied SOI-FET” and Proposal of CMOS without Vsub Bias
Wataru Yabuki; Jiro Ida; Takayuki Mori; Koichiro Ishibashi; Yasuo Arai
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE, 14 Oct. 2019
International conference proceedings - A 2.77 μW Ambient RF Energy Harvesting Using DTMOS Cross-Coupled Rectifier on 65 nm SOTB and Wide Bandwidth System Design
Thuy-Linh Nguyen; Yasuo Sato; Koichiro Ishibashi
MDPI Journal Electronics, MDPI, https://doi.org/10.3390/elect-10, 16 Sep. 2019, Peer-reviwed
Scientific journal, English - Precise Heart Rate Measurement Using Non-Contact Doppler Radear Assisted by Machine-Learning-Based Sleep Psture Estimation
Kotaro Higashi; Guanghao Sun; Koichiro Ishibashi
1, 1-4, 19 Jul. 2019, Peer-reviwed
International conference proceedings, English - Non-Contact Blood Pressure Measurement Scheme Using Doppler Readar
Tomoyuki Ohata; Koichiro Ishibashi; Guanghao Sun
1, 1-4, 19 Jul. 2019, Peer-reviwed
International conference proceedings, English - A Non-Contact Cardiopulmonary Measuring System using Medical Radar and FPGA
Cuong V. Nguyena; Truong Le Quanga; Trung Nguyen Vub; Hoi Le Thib; Kinh Nguyen Van; Thanh Han Trong; Tuan Do Trong; Guanghao Sund; Koichiro Ishibashid
1, 1-4, 19 Jul. 2019, Peer-reviwed
International conference proceedings, English - Beat Sensors for Smart Environment Monitoring Systems
Koichiro Ishibashi; Duangchak Manyvone; Miho Itoh, Van-Phuc; Hoang, Van-Lan Dao
1, 1-4, 21 Mar. 2019, Peer-reviwed
International conference proceedings, English - Long Battery Life IoT Sensing by Beat Sensors
Koichiro Ishibashi; Ryohei Takitoge; Duangchak Manyvone; Nobuto Ono; Shigeya Yamaguchi
1, 1-4, 19 Mar. 2019, Peer-reviwed
International conference proceedings, English - A non-contact infection screening system using medical radar and Linux-embedded FPGA: Implementation and preliminary validation
Cuong V. Nguyen; Truong Le Quang; Trung Nguyen Vu; Hoi Le Thi; Kinh Nguyen Van; Thanh Han Trong; Tuan Do Trong; Guanghao Sun; Koichiro Ishibashi
Informatics in Medicine unloked, 1, 1-4, 16 Mar. 2019, Peer-reviwed
Symposium, English - Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning
Xiaofeng Yang; Koki Kumugai; Guanghao Sun; Koichiro Ishibashi; Le Thi Hoi; Nguyen Vu Trung; Nguyen Van Kinh
SAS, 1, 1-4, 11 Mar. 2019, Peer-reviwed
International conference proceedings, English - First Experimental Confirmation of Transient Effect on Super Steep SS “PN-Body Tied SOI FET” with Pulse Measurements
H. Endo; J. Ida; T. Mori; K. Ishibashi; Y. Arai
sessionSi-Dev2-3, 1-3, 2019
International conference proceedings, English - First Experimental Confirmation of Ultralow Voltage Rectification by Super Steep Subthreshold Slope “PN-Body Tied SOI-FET” for High Efficiency RF Energy Harvesting and Ultralow Voltage Sensing
S. Momose; J. Ida; T. Yamada; T. Mori; K. Itoh; K. Ishibashi; Y. Arai
IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFEREN C E, 2018, 10.4, 15 Oct. 2018, Peer-reviwed
International conference proceedings, English - "A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors"
Koichiro Ishibashi; Shiho Takahashi
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018, 187-190, 09 Jul. 2018, Peer-reviwed
International conference proceedings, English - 83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks
Van-Trung NGUYEN; Ryo ISHIKAWA; Koichiro ISHIBASHI
IEICE Transactions on Electronics, IEICE, 2018, E101.C, 472-479, Jul. 2018, Peer-reviwed
Scientific journal, English - Diode characteristics of a super-steep subthreshold slope PN-body tied SOI-FET for energy harvesting applications
Takayuki Mori; Jiro Ida; Shun Momose; Kenji Itoh; Koichiro Ishibashi; Yasuo Arai
IEEE Journal of the Electron Devices Society, Institute of Electrical and Electronics Engineers Inc., 6, vol6, 565-570, 06 Apr. 2018, Peer-reviwed, In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope 'PN-body tied (PNBT) silicon-on-insulator field-effect transistor' are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.
Scientific journal, English - Gate controlled diode characteristics of super steep subthreshold slope PN-body tied SOI-FET for high efficiency RF energy harvesting
Shun Momose; Jiro Ida; Takayuki Mori; Takahiro Yoshida; Jumpei Iwata; Takashi Horii; Takahiro Furuta; Kenji Itoh; Koichiro Ishibashi; Yasuo Arai
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers Inc., 2018-, 2017, 1-3, 07 Mar. 2018, Gate controlled diode (GCD) characteristics with our newly proposed super steep subthreshold slope (SS) 'PN-Body Tied SOI-FET' was shown, for the first time, compared with the conventional diodes. It shows the super steep characteristics, the low leakage current and the sharp On-characteristics even on the ultralow voltage range of 50mV. The simple circuit simulations also indicated that the GCD with 'PN-Body Tied SOI-FET' will achieve the high efficiency rectification on the ultralow input power of the RF energy harvesting. Additionally, the slight shift of the voltage of the zero current was confirmed as a specific characteristics on this GCD.
International conference proceedings, English - Implementation of Condition-Aware Receiver-Initiated MAC Protocol to Realize Energy-Harvesting Wireless Sensor Networks,
Tatsuhiro Kawaguchi; Ryo Tanabe; Ryohei Takitoge; Koichiro Ishibashi; Koji Ishibashi
IEEE Consumer Communications & Networking Conference, *, *, 12 Jan. 2018, Peer-reviwed
International conference proceedings, English - Energy-Aware Receiver-Driven Medium Access Control Protocol for Wireless Energy-Harvesting Sensor Networks
Ryo Tanabe; Tatsuhiro Kawaguchi; Ryohei Takitoge; Koichiro Ishibashi; Koji Ishibashi
IEEE Consumer Communications & Networking Conference, IEEE Consumer Communications & Networking Conference, *, *, 12 Jan. 2018, Peer-reviwed
International conference proceedings, English - Continuous Cuffless Measurement of Systolic Blood Pressure using PPG and Doppler Radar
OHATA TOMOYUKI; ISHIBASHI KOICHIRO; SUN GUANGHAO
Transactions of Japanese Society for Medical and Biological Engineering, Japanese Society for Medical and Biological Engineering, Annual56, Abstract, S92-S92, 2018, In this study, we studied the method of estimating continuous blood pressure only in one part of the body using PPG or non-contact Doppler radar. We performed regression analysis considering relationship between time of one heartbeat cycle and systolic blood pressure. The time of one heartbeat cycle was acquired using PPG and Doppler radar. Since the obtained regression equation included individual differences, we obtained a regression equation that does not include individual differences by using the time of one heartbeat cycle and the systolic blood pressure at rest as individual parameters. Comparing the blood pressure estimated using this regression equation with the reference blood pressure, we obtained the correlation coefficient of 0.9, which was sufficiently high. The potential of non-contact blood pressure measurement using Doppler radar is also shown.
Japanese - Beat sensors IoT technology suitable for energy saving
Koichiro Ishibashi; Rhohei Takitoge; Shohei Ishigaki
Proceedings of 2017 7th International Conference on Integrated Circuits, Design, and Verification, ICDV 2017, Institute of Electrical and Electronics Engineers Inc., 2017-, 52-55, 12 Dec. 2017, Peer-reviwed, We have proposed IoT beat sensors in which wireless TX send only ID codes, and RX receivers the ID codes. The data acquired by the sensors are recovered by the interval time of the ID code in RX. The ID code transmissions are called as Beats so that the sensors are called as beat sensors. Beat sensor realizes low power, small size, and low cost sensors, which are large advantages as IoT sensors. This paper introduces the concept of the Beat Sensors, and describes Power Beat Sensor, DC Current Beat Sensor for use to reduce the electrical energy in Home and Buildings and so on.
International conference proceedings, English - LOW-POWER ENHANCED TEMPERATURE BEAT SENSOR WITH LONGER COMMUNICATION DISTANCE BY DATA-RECOVERY ALGORITHM
Ryohei Takitoge; Masataka Kishi; Koichiro Ishibashi
IEEE SENSORS2017, IEEE SENSORS 2017, 379-381, 29 Oct. 2017, Peer-reviwed
International conference proceedings, English - Field evaluation of an infectious disease/fever screening radar system during the 2017 dengue fever outbreak in hanoi, vietnam: a preliminary report
Guanghao Sun; Nguyen Vu Trung; Takemi Matsui; Koichiro Ishibashi; Tetsuo Kirimoto; Hiroki Furukawa; Le Thi Hoi; Nguyen Nguyen Huyen; Quynh Nguyen; Shigeto Abe; Yukiya Hakozaki
Journal of Infection, 75/6, 593-595, 24 Oct. 2017, Peer-reviwed
Scientific journal, English - A 0.148nJ/conversion 65nm SOTB Temperature Sensor LSI Using ThermistorDefined Current Source
Shinya Nii; Koichiro Ishibashi
S3SConference, 2017, 16 Oct. 2017
English - DC Current Beat: Wireless and Non-Invasive DC Current Sensing Scheme
Koichiro Ishibashi; Makoto Serizawa; Ryohei Takitoge; Shohei Ishigaki; Tsuyoshi Ishige
MDPI journals, 1, 4, 567-567, 24 Sep. 2017, Peer-reviwed, This paper presents a wireless and Non-invasive DC Current (DCC) sensing scheme as an IoT sensors. A RF module transmits only ID codes to a receiver, and the ID transmissions are called as “DCC Beat”. The interval time of DCC Beats depend on the inductance of ferrite clamp which is non-invasively installed at the wire of the DC current to be measured, so that the interval time corresponds to DC Current. The ID data transmission range reaches up to 50 m with 1.2 mW operating power using a 2.4 GHz RF module. DC current from 0.2 to 4 A can be measured within error of 5.7%.
International conference proceedings, English - Non-contact acquisition of respiration and heart rates using Doppler radar with time domain peak-detection algorithm
Xiaofeng Yang; Guanghao Sun; Koichiro Ishibashi
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS, Institute of Electrical and Electronics Engineers Inc., 2847-2850, 13 Sep. 2017, Peer-reviwed, The non-contact measurement of the respiration rate (RR) and heart rate (HR) using a Doppler radar has attracted more attention in the field of home healthcare monitoring, due to the extremely low burden on patients, unconsciousness and unconstraint. Most of the previous studies have performed the frequency-domain analysis of radar signals to detect the respiration and heartbeat frequency. However, these procedures required long period time (approximately 30 s) windows to obtain a high-resolution spectrum. In this study, we propose a time-domain peak detection algorithm for the fast acquisition of the RR and HR within a breathing cycle (approximately 5 s), including inhalation and exhalation. Signal pre-processing using an analog band-pass filter (BPF) that extracts respiration and heartbeat signals was performed. Thereafter, the HR and RR were calculated using a peak position detection method, which was carried out via LABVIEW. To evaluate the measurement accuracy, we measured the HR and RR of seven subjects in the laboratory. As a reference of HR and RR, the persons wore contact sensors i.e., an electrocardiograph (ECG) and a respiration band. The time domain peak-detection algorithm, based on the Doppler radar, exhibited a significant correlation coefficient of HR of 0.92 and a correlation coefficient of RR of 0.99, between the ECG and respiration band, respectively.
International conference proceedings, English - Review of Steep Subthreshold Slope Devices and its possibility for High Efficiency RF Energy Harvesting
Jiro IDA; Kenji ITOH; Koichiro ISHIBASHI
VJMW2017, 13 Jun. 2017, Invited, t The research status of steep subthreshold slope (SS) devices for LSI’s on the Ultra low power IoT systems is reviewed, and our
newly proposed super steep SS “PN- Body Tied SOI FET” is introduced. The diode technology for RF energy harvesting is also reviewed
and the possibility of the high efficiency rectification for the ultralow input on the RF energy harvesting are shown with our “PN- Body Tied
SOI FET”.
International conference proceedings, English - Power Beat and Temperature Beat Sensors — Precise, Low Cost, and Energy Harvesting Sensing Scheme for IoT Applications —
Koichiro ISHIBASHI; Ryohei TAKITOGE; Shohei ISHIGAKI
VJMW2017, 13 Jun. 2017, We have proposed Power Beat sensor and Temperature Beat sensor as energy harvesting wireless sensing scheme. This
paper reviews advantages of the proposed Beat Sensors in terms of accuracy, cost, and power which are inevitable
characteristics for IoT applications. We show at first time that leakage of electrical appliances can be measured by power beat
sensors
International conference proceedings, English - A 910nW Delta Sigma Modulator using 65nm SOTB Technology for Mixed Signal IC of IoT Applications,
Ishibashi Koichiro; Kikuchi Junya; Sugii Nobuyuki
ICICDT2017, Session F, 23 May 2017, Peer-reviwed, Invited
International conference proceedings, English - Short time and contactless virus infection screening system with discriminate function using doppler radar
Xiaofeng Yang; Koichiro Ishibashi; Toshiaki Negishi; Tetsuo Kirimoto; Guanghao Sun
Communications in Computer and Information Science, Springer Verlag, 791, 263-273, 2017, Peer-reviwed, Recently, infectious diseases, such as Ebola fever and Middle East respiratory syndrome, have spread worldwide. To conduct a highly accurate infection screening, our group is working on the development of a non-contact and hand-held infection screening system that can detect infected individuals within 5s. In this study, we propose a signal processing method to improve the measurement accuracy of the infection screening system. Body surface temperature, heartbeat, and respiration rates are detected by thermography and microwave radars. To evaluate the measurement accuracy, nine subjects (normal and pseudo-infection conditions) were tested with the proposed system in a laboratory. In this study, a linear discriminate function was used to detect pseudo-infection conditions. The detection accuracy was improved to 88.9%.
International conference proceedings, English - A 1.36 mu W 312-315 MHz synchronized-OOK receiver for wireless sensor networks using 65 nm SOTB CMOS technology
Minh-Thien Hoang; Nobuyuki Sugii; Koichiro Ishibashi
SOLID-STATE ELECTRONICS, PERGAMON-ELSEVIER SCIENCE LTD, 117, 161-169, Mar. 2016, Peer-reviwed, The paper presents a receiver design operating at 312-315 MHz frequency band for wireless sensor networks. The proposed architecture uses synchronized on-off-keying (S-OOK) modulation scheme, which includes clock information together with data, providing self-synchronization ability for the receiver without a separate clock and data recovery circuit. In addition, a new technique is also proposed to reduce active time of the RF font-end for better energy efficiency. The receiver architecture is verified by using discrete RF modules and FPGAs, then VLSI design is carried out on 65 nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology and simulated using SPICE models to illustrate effectiveness of the proposed architecture. Post-layout simulation shows -58.5 dBm sensitivity with 1.36 mu W and 8.39 mu W power consumption corresponding to 10 kbps and 100 kbps data rate, respectively. (C) 2015 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license.
Scientific journal, English - Temperature Beat: Persistent and Energy Harvesting Wireless Temperature Sensing Scheme
Ryohei Takitoge; Shohei Ishigaki; Tsuyoshi Ishige; Koichiro Ishibashi
2016 IEEE SENSORS, IEEE, 2016, Peer-reviwed, This paper presents a persistent and energy harvesting wireless temperature sensing scheme. Every time when the voltage is stored in a storage capacitor, the RF module transmits ID code to a receiver. The transmission of only ID code is called as "Temperature Beat", the cycle time of which corresponds to temperature. Time between Temperature Beat represents average temperature, so that it is not an intermittent but a persistent sensing. The size of the sensor node is 50 x 35 x 15mm and the energy for transmitting one Temperature Beat is 0.43mJ. Solar cell with lithium ion battery can be used to achieve energy harvesting operation. In experiments, this system can measure -21 similar to 90 degree C with accuracy of +/- 0.655 degree C with consuming 1.38mJ to transmit one Temperature Beat.
International conference proceedings, English - Design of-30dBm Sensitivity and Sub 10nW Wake-up Receiver for Wireless Sensor Networks Using Body Boost on 65nm SOTB Technology
Tsuyoshi Ishige; Koichiro Ishibashi
PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC), IEEE, 318-321, 2016, Peer-reviwed, This paper presents a wake-up receiver (WuRx) for wireless sensor networks, which can wake up devices connected to WuRx when it receives RF signals. The proposed WuRx consists of a LC passive voltage booster at 920 MHz, a voltage multiplier and a Schmitt trigger comparator. In the simulation, the sensitivity is -30 dBm and the power consumption is 6.7 nW of the comparator. The voltage multiplier is designed for 65 nm SOTB (Silicon on Thin Buried Oxide) technology for low voltage operation.
International conference proceedings, English - A Small-Size Energy-Harvesting Electric Power Sensor for Implementing Existing Electrical Appliances Into HEMS
Yuki Tsunoda; Chikara Tsuchiya; Yuji Segawa; Hajime Sawaya; Minoru Hasegawa; Shohei Ishigaki; Koichiro Ishibashi
IEEE SENSORS JOURNAL, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 16, 2, 457-463, Jan. 2016, Peer-reviwed, This paper presents a small-size electric power sensor that can be installed at an outlet to sense the power of electrical appliances whose plugs are inserted into the outlet. The data for the power consumption of the appliance and the power for the microcontroller unit (MCU) are obtained by an electromagnetic induction method, so that it can be implemented without any electrical work. The sensitivity of the power sensor is 1 W, and the power for the MCU can be generated from an appliance power of 23 W. The sensor itself consumes 3.75 mW. This sensor can be used to measure the power consumption of the existing electrical appliances.
Scientific journal, English - SOTB technology, which enables perpetually reliable CPU for IoT applications
Koichiro Ishibashi; Nobuyuki Sugii; Kazutoshi Kobayashi; Tomoaki Koide; Hiroki Nagatomi; Shiro Kamohara
2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., \DOI: 10.1109/E3S, 1-3, 24 Nov. 2015, Peer-reviwed, Sensors and wearable systems are expanding to make the IoT era. Requirements of the devices to realize the expansion of the systems are low-power LSIs which can operate eternally with energy harvesting power sources. The LSI should operate fast enough to deal with the data, followed by sleep mode to save the energy. The data during sleep mode should be reliably stored for the next intermittent operation.
International conference proceedings, English - Designs of Ultra-Low-Power and Ultra-Low-Leakage 65nm-SOTB LSI for IoT Applications
Koichiro Isibashi
IEEE S3S Conference 2015, IEEE S3S Conference 2015, 05 Oct. 2015, Peer-reviwed
International conference proceedings, English - A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro Ishibashi; Nobuyuki Sugii; Shiro Kamohara; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E98C, 7, 536-543, Jul. 2015, Peer-reviwed, A 32bit CPU, which can operate more than 15 years with 220mAH Li battery, or eternally operate with an energy harvester of in-door light is presented. The CPU was fabricated by using 65nm SOTB CMOS technology (Silicon on Thin Buried oxide) where gate length is 60nm and BOX layer thickness is 10nm. The threshold voltage was designed to be as low as 0.19V so that the CPU operates at over threshold region, even at lower supply voltages down to 0.22V. Large reverse body bias up to -2.5V can be applied to bodies of SOTB devices without increasing gate induced drain leak current to reduce the sleep current of the CPU. It operated at 14MHz and 0.35V with the lowest energy of 13.4 pJ/cycle. The sleep current of 0.14 mu A at 0.35V with the body bias voltage of -2.5V was obtained. These characteristics are suitable for such new applications as energy harvesting sensor network systems, and long lasting wearable computers.
Scientific journal, English - A 27.6 mu W 315 MHz low-complexity OOK receiver with on-off RF front-end
Minh-Thien Hoang; Nobuyuki Sugii; Koichiro Ishibashi
IEICE ELECTRONICS EXPRESS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 12, 7, pp. 20150206, Apr. 2015, Peer-reviwed, This paper presents a receiver design with the on-off keying (OOK) modulation at 315 MHz frequency. In this design, we propose a new architecture for the receiver to achieve low complexity with a solution to reduce total power consumption significantly. The operation of the proposed architecture is verified using available RF front-end circuits and a field-programmable-gate-array (FPGA) device. Circuit of the receiver is designed by using SPICE models of 65 nm Silicon On Thin Buried Oxide (SOTB) CMOS technology. By simulation, the receiver achieves -76 dBm sensitivity, consumes 27.6 mu W from 1V supply voltage with data rate up to 200 Kbps.
Scientific journal, English - A Study on Ultra-low Power and High Sensitibity CMOS RF Receiver for Wireless Sensor Networks
Hoang Minh Thien
2015, 2015
English - Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process
Duc-Hung Le; Nobuyuki Sugii; Shiro Kamohara; Xuan-Thuan Nguyen; Koichiro Ishibashi; Cong-Kha Pham
2015 International Conference on IC Design & Technology (ICICDT), IEEE, IEEE Region 10 ATC 2014, 2015, Peer-reviwed, In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282 mu W at the operation voltage 0.55V and operation frequency 200MHz.
International conference proceedings, English - Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process
Duc-Hung Le; Nobuyuki Sugii; Shiro Kamohara; Xuan-Thuan Nguyen; Koichiro Ishibashi; Cong-Kha Pham
2015 International Conference on IC Design & Technology (ICICDT), IEEE, Design and Technology, 2015, Peer-reviwed, In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282 mu W at the operation voltage 0.55V and operation frequency 200MHz.
International conference proceedings, English - Power Beat: A Low-cost and Energy Harvesting Wireless Electric Power Sensing for BEMS
Shohei Ishigaki; Koichiro Ishibashi
2015 IEEE INTERNATIONAL CONFERENCE ON BUILDING ENERGY EFFICIENCY AND SUSTAINABLE TECHNOLOGIES (ICBEST), IEEE, ICBEST2015, 28-32, 2015, Peer-reviwed, This paper presents a wireless power sensing for existing electrical appliances in buildings and houses. A wireless transmitter operates with power harvested from the current flowing in the electrical appliances. Every time when the voltage is stored in a storage capacitor, the RF module transmits ID code to a receiver. The transmission forms Power Beat which includes information of the power of the appliance. The power of the electrical appliance is calculated by the cycle time of the transmission. The transmitter operates when the electrical appliance works, so that total energy of measurement system is low, even when the numbers of the transmitters in a building or houses become large. The transmitter doesn't need power sensing devices, achieving low cost of the system. In experiments, this system can measure appliances power down to 20W with +/- 10% accuracy.
International conference proceedings, English - A 400triV 059m. Lowpower CAM-based Pattern Matching System on 65nm SOTB Process
Duc-Hung Lei; Nobuyuki Sugii; Shiro Kamohara; Hong-Thu Nguyen; Koichiro Ishibashi; Cong-Kha Pham
TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE, IEEE, TENCON 2015, 2015, Peer-reviwed, A CAA-based matching system for fast exact pattern matching is implemented on AMC, using 65nm SOTB process, for Ver.), low power consumption. I he system has a simple structure, which consists of Content 'Addressable Nlemory (( AM), AND, SHIFT, and an FYI!, does not employ Central Processor Unit ((Pt) as well as complicated algorithms. We take advantage ofCtI which has an ability of parallel multi -match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using any search principles. In this paper, the system operates at 4006V, power consumption 0.59m%% using SOl B 65nm process.
International conference proceedings, English - Low Power Channel Scanning with Contiki's IPv6 Stack for Wireless Sensor Network
Tran Ngoc Thinh; Tu Nguyen; Bui Van Hiev; Koichiro Ishibashi
ACOMP2014, ACOMP2014, 20 Nov. 2014, Peer-reviwed
International conference proceedings, English - A 0.75V 0.574mW 2.16GHz - 3.2GHz Differential Multipass Ring Oscillator on 65nm SOTB CMOS Technology
Minh-Thien Hoang; Nobuyuki Sugii; Koichiro Ishibashi
ICDV 2014, ICDV 2014, 14 Nov. 2014, Peer-reviwed
International conference proceedings, English - Ultralow-power SOTB CMOS technology operating down to 0.4 V
Nobuyuki Sugii; Yoshiki Yamamoto; Hideki Makiyama; Tomohiro Yamashita; Hidekazu Oda; Shiro Kamohara; Yasuo Yamaguchi; Koichiro Ishibashi; Tomoko Mizutani; Toshiro Hiramoto
Journal of Low Power Electronics and Applications, MDPI AG, 4, 2, 65-76, 24 Apr. 2014, Peer-reviwed, Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB's features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The "Perpetuum-Mobile" micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. © 2014 by the authors
licensee MDPI, Basel, Switzerland.
Scientific journal, English - Speed enhancement at V-dd=0.4V and random tau(pd) variability reduction and analyisis of tau(pd) variability of silicon on thin buried oxide circuits
Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Hidekazu Oda; Nobuyuki Sugii; Koichiro Ishibashi; Yasuo Yamaguchi
JAPANESE JOURNAL OF APPLIED PHYSICS, IOP PUBLISHING LTD, 53, 4, Apr. 2014, Peer-reviwed, Ring oscillator characteristics of silicon on thin buried oxide (SOTB) were investigated at V-dd down to 0.4V. It was demonstrated that both the propagation delay (tau(pd)) and energy-delay (ED) product of SOTB were smaller than those of bulk devices due to its steeper subthreshold swing. It was found that the tau(pd) variability of SOTB is dominated by global variability because local variability is small due to the intrinsic channel. The origin of tau(pd) variability was analyzed by taking the transistor dc characteristics into account. It was found that the tau(pd) variability of SOTB is caused by the global drive current variability because the effect of resistance (or effective drain current I-eff) is much larger than that of capacitance with V-dd reduction. The tau(pd) variability is mainly caused by the global drive-current variability and thus can be easily reduced by die-to-die substrate bias voltage control. (C) 2014 The Japan Society of Applied Physics
Scientific journal, English - Speed enhancement at V
Makiyama Hideki; Yamamoto Yoshiki; Shinohara Hirofumi; Iwamatsu Toshiaki; Oda Hidekazu; Sugii Nobuyuki; Ishibashi Koichiro; Yamaguchi Yasuo
Jpn. J. Appl. Phys., Institute of Physics, 53, 4, 04EC07, 12 Feb. 2014
English - 低電圧・低電力LSI技術の最新動向
石橋孝一郎
電子情報通信学会和文論文誌, Vol.J97-C, No.1, Jan. 2014
Scientific journal, Japanese - A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14 mu A Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology
Koiehiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguehi; Hidekazu Oda; Takumi Hasegawa; Shinobu Okanishi; Hiroshi Yanagita; Shiro Kamohara; Masaru Kadoshima; Keiiehi Maekawa; Tomohiro Yamashita; Duc-Hung Le; Takumu Yomogita; Masaru Kudo; Kuniaki Kitamori; Shuya Kondo; Yuuki Manzawa
2014 IEEE COOL CHIPS XVII, IEEE, Cool Chips XVII, 2014, Peer-reviwed, A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14 mu A sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.
International conference proceedings, English - Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era
Shiro Kamohara; Nobuyuki Sugii; Yoshiki Yamamoto; Hideki Makiyama; Tomohiro Yamashita; Takumi Hasegawa; Shinobu Okanishi; Hiroshi Yanagita; Masaru Kadoshima; Keiichi Maekawa; Hitoshi Mitani; Yasushi Yamagata; Hidekazu Oda; Yasuo Yamaguchi; Koichiro Ishibashi; Hideharu Amano; Kimiyoshi Usami; Kazutoshi Kobayashi; Tomoko Mizutani; Toshiro Hiramoto
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, IEEE, 2014 Symposia on VLSI Technolo, 2014, Peer-reviwed, Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named " Perpetuum Mobile," has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.
International conference proceedings, English - A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Shiro Kamohara; Nobuyuki Sugil; Koichiro Ishibashi; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham
2014 IEEE HOT CHIPS 26 SYMPOSIUM (HCS), IEEE, Hot Chips 2014, 2014, Peer-reviwed
International conference proceedings, English - A 53 mu W-82dBm Sensitivity 920MHz OOK Receiver Design Using Bias Switch Technique on 65nm SOTB CMOS Technology
Hoang Minh Thien; Nobuyuki Sugii; Koichiro Ishibashi
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE, 2014 IEEE S3S Conference, 2014, Peer-reviwed, This paper presents an ultra-low power receiver design at 920MHz. We proposed a receiver architecture, in which bias switch technique is applied to reduce power consumption significantly. The receiver was simulated and laid out on 65nm SOTB CMOS technology, consuming only 53uW at 0.6V supply voltage. It achieves a sensitivity of -82dBm with a data rate of 10 - 100 kbps.
International conference proceedings, English - A 361nA Thermal Run-away Immune VBB Generator using Dynamic Substrate Controlled Charge Pump for Ultra Low Sleep Current Logic on 65nm SOTB
Hiroki Nagatomi; Nobuyuki Sugii; Shiro Kamohara; Koichiro Ishibashi
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE, 2014 IEEE S3S Conference, 2014, Peer-reviwed, This paper proposed an on-chip low power Body Bias Generator (VBBGEN) for ultra low leakage at 65nm SOTB (Silicon on Thin Buried Oxide) logic circuits at sleep mode. In the results of post layout simulation, the VBBGEN can generate and apply up to -2V body bias at a supply voltage of 0.5V with a current consumption of less than 361nA. By using the VBBGEN, it is expected that sleep current of CPU on SOTB is decreased by more than two orders of magnitude. In addition, the VBBGEN also has a function that prevents thermal run away of SOTB logic circuits.
International conference proceedings, English - A Card Size Energy Harvesting Electric Power Sensor for Implementing Existing Electric Appliances into HEMS
Yuki Tsunoda; Chikara Tsuchiya; Yuji Segawa; Hajime Sawaya; Minoru Hasegawa; Koichiro Ishibashi
2014 IEEE SENSORS, IEEE, IEEE SENSORS 2014, 2014, Peer-reviwed, This paper presents a card size electric power sensor, which can be installed at the surface of an outlet and senses power of electric appliances whose plug is set to the outlet. The data of the power and the power for MCU is obtained by electromagnetic induction method so that it can be implemented without any work. The sensitivity of the power sensor is 6W, and the power for MCU can be generated from appliances power of 40W. This sensor can be used for measuring the power consumption of existing electric appliances.
International conference proceedings, English - Perpetuum-Mobile Sensor Network Systems using a CPU on 65nm SOTB CMOS Technology
Koichiro Ishibashi; Cong-Kha Pham; Nobuyuki Sugii
ICDV 2014, 2014, Peer-reviwed
International conference proceedings, English - A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Shiro Kamohara; Nobuyuki Sugil; Koichiro Ishibashi; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham
2014 IEEE HOT CHIPS 26 SYMPOSIUM (HCS), IEEE, Vol.E98-C, No.7, 536-543, 2014, Peer-reviwed
International conference proceedings, English - A Card Size Energy Harvesting Electric Power Sensor for Implementing Existing Electric Appliances into HEMS
Yuki Tsunoda; Chikara Tsuchiya; Yuji Segawa; Hajime Sawaya; Minoru Hasegawa; Koichiro Ishibashi
2014 IEEE SENSORS, IEEE, Vol.16, No. 2, 457-463, 2014, Peer-reviwed, This paper presents a card size electric power sensor, which can be installed at the surface of an outlet and senses power of electric appliances whose plug is set to the outlet. The data of the power and the power for MCU is obtained by electromagnetic induction method so that it can be implemented without any work. The sensitivity of the power sensor is 6W, and the power for MCU can be generated from appliances power of 40W. This sensor can be used for measuring the power consumption of existing electric appliances.
International conference proceedings, English - An ultra-low power LNA design using SOTB CMOS devices
Hoang Minh Thien; Koichiro Ishibashi
2013 Thailand-Japan Micro Wave 2013, 2013 Thailand-Japan Micro Wave, Dec. 2013, Peer-reviwed
International conference proceedings, English - A 4pA/Gate Sleep Current 65nm SOTB Logic Gates Using On-chip VBB Generator for Energy Harvesting Sensor Network Systems
Hiroki Nagatomi; Le Duc-Hung; Cong-Kha Pham; Nobuyuki Sugii; Shirou Kamohara; Toshiaki; Iwamatsu; Koichiro Ishibashi
ICDV 2013, ICDV 2013, Nov. 2013, Peer-reviwed
International conference proceedings, English - Ultralow-Voltage Operation SOTB Technology toward Energy Efficient Electronics
N. Sugii; T. Iwamatsu; Yamamoto; H. Makiyama; H. Shinohara; H; Od; S; Kamohara; Y. Yamaguchi; T. Mizutani; K. Ishibashi; T. Hiramoto
International Solid-State Devices and Materials, International Solid-State Devi, Sep. 2013
Scientific journal, English - Speed Enhancement at Vdd = 0.4 V and Randam τpd Variability Reduction of Silicon on Thin Buried Oxide (SOTB)
H. Makiyama, Y; Yamamoto; H. Shinohara; T. Iwamatsu; H. Oda, N; Sugii; K. Ishibashi and Y; Yamaguchi
International Solid-State Devices and Materials, International Solid-State Devi, Sep. 2013, Peer-reviwed
International conference proceedings, English - On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Jinmyoung Kim; Toru Nakura; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E96C, 4, 560-567, Apr. 2013, Peer-reviwed, This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 mu m CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
Scientific journal, English - Continuous Challenges for Ultra-Low Power LSI - Technologies, and Their Impact to ITC Societies
Koichiro Ishibashi
IEICE Vietnam Section Lecture Meeting on ICT and Inauguration Ceremony, IEICE Vietnam section, IEICE Vietnam Section Lecture, Mar. 2013, Peer-reviwed
International conference proceedings, English - V-min=0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB) - How is the application with "Perpetuum-Mobile" micro-controller with SOTB?
N. Sugii; T. Iwamatsu; Y. Yamamoto; H. Makiyama; H. Shinohara; H. Oda; S. Kamohara; Y. Yamaguchi; K. Ishibashi; T. Mizutani; T. Hiramoto
2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), IEEE, IEEE S3S Conference 2013, 2013, Peer-reviwed, Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the near-or sub-Vth operation is effective in reducing energy per operation of CMOS circuits, its slow operation speed can miss a chance to be used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultra-low-power (ULP) electronics because of its small variability and back-bias control. This paper describes our results on the ULV operation of SRAM and ring oscillator (RO) circuits and shows the operation speed is now sufficiently high for many ULP applications. The "Perpetuum-Mobile" micro-controllers operating at similar to 0.4 V are expected to be implemented in many applications such as the internet of things.
International conference proceedings, English - A 44 mu W/10MHz Minimum Power Operation of 50K Logic Gate using 65nm SOTB Devices with Back Gate Control
Shotaro Morohashi; Nobuyuki Sugii; Toshiaki Iwamatsu; Shiro Kamohara; Yudai Kato; Cong-Kha Pham; Koichiro Ishibashi
2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), IEEE, 2013 SOI-3DI Subthreshold Micr, 2013, Peer-reviwed, Performance, leakage and E-min on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44 mu W at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.
International conference proceedings, English - Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation
H. Makiyama; Y. Yamamoto; H. Shinohara; T. Iwamatsu; H. Oda; N. Sugii; K. Ishibashi; T. Mizutani; T. Hiramoto; Y. Yamaguchi
Technical Digest - International Electron Devices Meeting, IEDM, 2013 IEDM Technica Program, 33.2.4, 2013, Peer-reviwed, Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V. © 2013 IEEE.
International conference proceedings, English - A Challenge to Perpetuum Computing using SOTB Technology
Koichiro Ishibashi
ACOMP 2013, ACOMP, ACOMP 2013, 2013, Peer-reviwed
International conference proceedings, English - Sleep Mode Implementation to ZigBee Router Devices for Wireless Sensor Networks
Ryouta SHIRONO; VU Trong Thien; Kohichiro ISHIBASHI
ICDV 2012, ICDV 2012, Aug. 2012, Peer-reviwed
International conference proceedings, English - On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E95C, 4, 643-650, Apr. 2012, Peer-reviwed, Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.
Scientific journal, English - An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor
Kazuo Otsuga; Masafumi Onouchi; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa
International System on Chip Conference, 25th IEEE International System, 11-14, 2012, Peer-reviwed, We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm<
sup>
2<
/sup>
. To suppress the AC voltage drop due to large load transient (LLT), we developed a LLT control method using dynamic sampling clock frequency scaling scheme. The measurement results show that the AC voltage drop can be suppressed to 50%. The peak efficiency is 99% at 250 mA. © 2012 IEEE.
International conference proceedings, English - On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E94C, 4, 511-519, Apr. 2011, Peer-reviwed, This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 mu m CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100k-gate blocks, which is 7.1X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.
Scientific journal, English - Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), IEEE, 2011 IEEE 14th International S, 111-114, 2011, Peer-reviwed, This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18 mu m CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
International conference proceedings, English - On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
European Solid-State Circuits Conference, 37th European Solid-State Circ, 183-186, 2011, Peer-reviwed, Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4x boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively. © 2011 IEEE.
International conference proceedings, English - A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process
Masafumi Onouchi; Kazuo Otsuga; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, IEEE A-SSCC 2011, 37-40, 2011, Peer-reviwed, A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage power-MOS transistors. The LDO occupies only 0.057 mm 2 area using 40-nm CMOS technology, and covers a wide range of load currents from 400 μA to 250 mA. The response time is only 0.07 μs. © 2011 IEEE.
International conference proceedings, English - Low Power Technologies and their impact on ITC Societies
Koichiro Ishibashi
The 2011 International Conference on Integrated Circuits and Devices in Vietnam, IEICE, IEEE ICDV 2011, The 2011 International Confere, 2011, Peer-reviwed
International conference proceedings, English - A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS
Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 45, 11, 2312-2320, Nov. 2010, Peer-reviwed, A wide-range voltage-and-frequency clock synchronizer (WRCS) for maintaining synchronization during dynamic voltage-and-frequency scaling was developed. The key feature of the WRCS is short-range skew measurement based on a predictive- delay-adjustment (PDA) scheme. The short-range skew measurement results in reduction of the area of the WRCS by 77%, that is, the area of the fabricated WRCS in a 40-nm CMOS process is only 5.65 x 10(-3) mm(2). In the case of large voltage variation (0.8-1.55 V) and wide frequency range (100 MHz-1 GHz), measured skew is suppressed to the lowest percentage yet reported, namely, less than 6.8% of clock period. Moreover, current consumption of the WRCS is only 0.48 mA under 1.1-V 100-MHz operation.
Scientific journal, English - Resonant Supply Noise Canceller utilizing Parasitic Capacitance of Sleep Blocks
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, IEEE, VLSI Circuits symposium 2010, 119-+, 2010, Peer-reviwed, This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18 mu m CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.
International conference proceedings, English - LSI industry requirement to SOI for mobile applications
K. Ishibashi
the 3rd FDSOI Workshop, the 3rd FDSOI Workshop, 2010, Peer-reviwed
International conference proceedings, English - A Low-Power Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control
Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), IEEE, A-SSCC 2009, 85-88, 2009, Peer-reviwed, A "wide-range voltage-and-frequency clock synchronizer" (WRCS) for maintaining synchronization during voltage-scaling transition during dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the WRCS is so-called predictive-delay-adjustment (PDA) scheme based on a relative skew measure. The PDA scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65x10(-3) mm(2). It was demonstrated for the first time that measured jitter is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8 - 1.55 V) and wide frequency range (100 MHz - 1 GHz). Moreover, current dissipation of the WRCS is only 0.48 mA at 1.1-V 100-MHz operation.
International conference proceedings, English - Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs
Yusuke Kanno; Kenichi Yoshizumi; Yoshihiko Yasu; Koichiro Ishibashi; Hiroyuki Mizuno
2008 IEEE SYMPOSIUM ON VLSI CIRCUITS, IEEE, 115-+, 2008, Peer-reviwed, We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44% voltage drop with about 10% area overhead in a 65 nm CMOS. This DVB; method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.
International conference proceedings, English - A 65 nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and Cu E-trim fuse for known good die
Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; Masakazu Okada; Atsushi Ishii; Tsutomu Yoshihara; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 43, 1, 96-108, Jan. 2008, Peer-reviwed, We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mu m(2) using 65 nm technology.
Scientific journal, English - Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs
Yusuke Kanno; Kenichi Yoshizumi; Yoshihiko Yasu; Koichiro Ishibashi; Hiroyuki Mizuno
2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, IEEE, VLSI Circuit Symposium, 148-+, 2008, Peer-reviwed, We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44% voltage drop with about 10% area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.
International conference proceedings, English - Hot-CarrierAC Lifetime Enhancement due to Wire Resistance Effect (WRE) in 45nm CMOS Circuits
N. Mizuguchi; K. Takeuchi; H. Tobe; P. Lee; K. Ishibashi
SSDM2008, SSDM2008, 2008, Peer-reviwed
International conference proceedings, English - Adaptive Design of SRAM Memory Cells
K. Ishibashi
International Electron Devices Meeting, IEEE IEDM 2007, Special Evening Session, International Electron Devices, Dec. 2007, Peer-reviwed
International conference proceedings, English - A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits
Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; Masahide Inuishi; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinobara
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 42, 4, 820-829, Apr. 2007, Peer-reviwed, In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.
Scientific journal, English - Substrate-noise and random-variability reduction with self-adjusted forward body bias
Yoshihide Komatsu; Koichiro Ishibashi; Makoto Nagata
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E90C, 4, 692-698, Apr. 2007, Peer-reviwed, This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability sigma(I-ds) by 23.2-57.9%.
Scientific journal, English - A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits
Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; Masahide Inuishi; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinobara
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 42, 4, 820-829, Apr. 2007, Peer-reviwed, In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.
Scientific journal, English - Substrate-noise and random-variability reduction with self-adjusted forward body bias
Yoshihide Komatsu; Koichiro Ishibashi; Makoto Nagata
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E90C, 4, 692-698, Apr. 2007, Peer-reviwed, This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability sigma(I-ds) by 23.2-57.9%.
Scientific journal, English - Adaptive body bias techniques for low power SOC
K. Ishibashi
International Solid-State Circuits Conference, IEEE ISSCC 2007 Microprocessor Forum, International Solid-State Circ, Feb. 2007, Peer-reviwed
International conference proceedings, English - A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die
Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; Masakazu Qkada; Atsushi Ishii; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 485-617, 2007, A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%. © 2007 IEEE.
International conference proceedings, English - An adaptive design of SRAM memory cell
Koichiro Ishibashi
Technical Digest - International Electron Devices Meeting, IEDM, IEEE IEDM 2007, Special Evening Session, International Electron Devices, 646, 2007, Peer-reviwed
International conference proceedings, English - A 1.92 mu s-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
Kazuk Fukuoka; Osamu Ozawa; Ryo Mon; Yasuto Igarashi; Toshio Sasaki
2007 Symposium on VLSI Circuits, Digest of Technical Papers, JAPAN SOCIETY APPLIED PHYSICS, VLSI Circuit Symposium 2007, 128-129, 2007, Peer-reviwed, A technique for controlling rush cur-rent and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 mu s and leakage current is reduced by 96.9% in an application CPU domain. Probing g the rush current indicated accurate control by the technique.
International conference proceedings, English - Adaptive body bias techniques for low power SOC
K. Ishibashi
Microprocessor Forum, Microprocessor Forum, 2007, Peer-reviwed
International conference proceedings, English - Adaptive body bias techniques for low power SOC
K. Ishibashi
" in the special evening session” Chip Breakthroughs and Address Circuit/Device Interactions, " in the special evening sessi, 2007, Peer-reviwed
International conference proceedings, English - Low Power SOC Design using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for sub-100-nm LSTP technology
OZAWA Osamu; FUKUOKA Kazuki; IGARASHI Yasuto; KURAISHI Takashi; YASU Yosihiko; MAKI Yukio; IPPOSHI Takashi; OCHIAI Toshihiko; SHIRAHATA Masayoshi; ISHIBASHI Koichiro
ITE technical report, 映像情報メディア学会, 30, 65, 115-119, 14 Dec. 2006, Peer-reviwed
International conference proceedings, Japanese - Low-voltage and low-power logic, memory, and analog circuit techniques for SoCs using 90 nm technology and beyond
K Ishibashi; T Fujimoto; T Yamashita; H Okada; Y Arima; Y Hashimoto; K Sakata; Minematsu, I; Y Itoh; H Toda; M Ichihashi; Y Komatsu; M Hagiwara; T Tsukada
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E89C, 3, 250-262, Mar. 2006, Peer-reviwed, Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-pA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.
Scientific journal, English - Soft error hardened latch scheme with forward body bias in a 90-nm technology and beyond
Y Komatsu; Y Arima; K Ishibashi
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E89C, 3, 384-391, Mar. 2006, Peer-reviwed, This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.
Scientific journal, English - Soft error hardened latch scheme with forward body bias in a 90-nm technology and beyond
Y Komatsu; Y Arima; K Ishibashi
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E89C, 3, 384-391, Mar. 2006, Peer-reviwed, This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.
Scientific journal, English - Circuit technologies for reducing the power of SOC and issues on transistor models
Koichiro Ishibashi; Shigeki Ohbayashi; Katsumi Eikyu; Motoaki Tanizawa; Yasumasa Tsukamoto; Kenichi Osada; Masayuki Miyazaki; Masanao Yamaoka
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, IEEE, International Electron Devices, 882-+, 2006, Peer-reviwed, The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability.
International conference proceedings, English - A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
S. Ohbayashi; M. Yabuuchi; K. Nii; Y. Tsukamoto; S. Imaoka; Y. Oda; M.Igarashi; M. Takeuchi; H. Kawashima; H. Makino; Y. Yamaguchi; K. Tsukamoto; M. Inuishi; H. Makino; K. Ishibashi; H. Shinohara
VLSI Circuit Symposimu 2006, VLSI Circuit Symposimu 2006, 2006, Peer-reviwed
International conference proceedings, English - A 65nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
K. Nii; Y. Masuda; M. Yabuuchi; Y. Tsukamoto; S. Ohbayashi; S. Imaoka; M. Igarashi; K. Tomita; N. Tsuboi; H. Makino; K. Ishibashi; H. Shinohara
VLSI Circuit Symposium 2006, VLSI Circuit Symposium 2006, 2006, Peer-reviwed
International conference proceedings, English - Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability
Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2005, 398-405, 2005, 6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ V_Local). To achieve high-yield SRAM arrays in presence of random σV_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability. © 2005 IEEE.
International conference proceedings, English - 0.5V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process
M Ichihashi; H Toda; Y Itoh; K Ishibashi
2005 Symposium on VLSI Circuits, Digest of Technical Papers, JAPAN SOCIETY APPLIED PHYSICS, Symp. VLSI Circuits 2005, 366-369, 2005, Peer-reviwed, Asymmetric three-Tr. cell (ATC) DRAM which has one P-and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90nm technology dissipates 180 mu A in refresh current at 1 mu s cycle refresh on 1 Mb with SG mode.
International conference proceedings, English - Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability
Y Tsukamoto; K Nii; S Imaoka; Y Oda; S Ohbayashi; T Yoshizawa; H Makino; K Ishibashi; H Shinohara
ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, IEEE, ICCAD 2005, 398-405, 2005, Peer-reviwed, 6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (sigma v_(Local)) To achieve high-yield SRAM arrays in presence of random sigma v-(Local) component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.
International conference proceedings, English - 0.4-v logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme
M Yamaoka; K Osada; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 39, 6, 934-940, Jun. 2004, Peer-reviwed, We designed a, logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-muW power dissipation, and 0.9-muA standby current.
Scientific journal, English - 3-d device modeling for SRAM soft-error immunity and tolerance analysis
K Yamaguchi; Y Takemura; K Osada; K Ishibashi; Y Saito
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 51, 3, 378-388, Mar. 2004, Peer-reviwed, Soft-error tolerance of static random-access memory (SRAM) devices has been predicted by using three-dimensional (3-D) and time-dependent device simulation in conjunction with circuit simulation. An inverter model developed for 3-D device simulation is described, along with the analysis of the inverters device response as a function of time. The output thus obtained was applied as an input voltage source in circuit simulation of unit SRAM cell and the stability of this bistable circuit is studied on that basis. The effects on soft-error immunity of changes in alpha-particle injection conditions and in load resistance and capacitance are described.
The validity of the presented model is examined through comparison of the bit-error-rate dependence on incident angle of alpha particles to that of measured rates. To simulate the angular dependence, we introduce statistical distribution models for alpha-particle energy, position of incidence on the device surface, and angle of incident. Results of device/circuit simulation carried out with many sets of energy, position, and angle are presented. Reasonable agreement between results of simulation and experimental data without the use of adjustment parameters is demonstrated.
A map of soft-error tolerance on the CR plane with critical charge Q(c) as a parameter is presented and its derivation explained. An analytic expression for the tolerance is clarified by proposing an equivalent circuit model for the simulation of alpha-particle injection at the output node in an inverter circuit. Inverter modeling is shown to be essential to obtaining SRAM soft-error tolerance to high degrees of accuracy.
Scientific journal, English - Low Power Technology Development at STARC
Koichiro Ishibashi
The Second International Workshop on Nanoelectronics for Terra-bit Information Processing, The Second International Works, Jan. 2004, Peer-reviwed
International conference proceedings, English - Cosmic-ray immune latch circuit for 90nm technology and beyond
Y Arima; T Yamashita; Y Komatsu; T Fujimoto; K Ishibashi
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, IEEE, 47, 492-493, 2004, Peer-reviwed
International conference proceedings, English - CPU消費電力削減のための周波数-電圧協調型電力制御方式の設計ルールとフィードバック予測方式による適用
十山圭介; 三坂智; 相坂一夫; 在塚俊之; 内山邦男; 石橋孝一郎; 川口博; 桜井貴康
電子情報通信学会論文誌 D-I, Vol.J87-D-I, No.4, pp.452-461, 2004, Peer-reviwed
Scientific journal, Japanese - A soft-error hardened latch scheme for SoC in a 90nm technology and beyond
Y Komatsu; Y Arima; T Fujimoto; T Yamashita; K Ishibashi
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, IEEE, 2004 IEEE Custom Integrated Ci, 329-332, 2004, Peer-reviwed, In this paper, we proposed a soft-error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130nm 2-well, and also 90nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using alpha-particles, and 1-order higher immunity through neutron irradiation.
International conference proceedings, English - An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs
T Tsukada; Y Hashimoto; K Sakata; H Okada; K Ishibashi
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, IEEE, 47, 160-161, 2004, Peer-reviwed
International conference proceedings, English - An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs
T Tsukada; Y Hashimoto; K Sakata; H Okada; K Ishibashi
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, IEEE, 47, 160-161, 2004, Peer-reviwed
International conference proceedings, English - Low power SoC project at STARC: low voltage and high speed digital and analog circuits
K. Ishibashi
Seminar @IMEC, Seminar @IMEC, 07 Nov. 2003, Peer-reviwed
International conference proceedings, English - 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors
K Osada; Y Saitoh; E Ibe; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 38, 11, 1952-1957, Nov. 2003, Peer-reviwed, Tunnl-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-mum CMOS technology showed per-cell standby-current values of 16.7 fA at 25 degreesC and 101.7 fA at 90 degreesC. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.
Scientific journal, English - 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors
K Osada; Y Saitoh; E Ibe; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 38, 11, 1952-1957, Nov. 2003, Peer-reviwed, Tunnl-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-mum CMOS technology showed per-cell standby-current values of 16.7 fA at 25 degreesC and 101.7 fA at 90 degreesC. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.
Scientific journal, English - Failure analysis of 6T SRAM on low-voltage and high-frequency operation
S Ikeda; Y Yoshida; K Ishibashi; Y Mitsui
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 50, 5, 1270-1276, May 2003, Peer-reviwed, Careful analysis of SRAM bit failure at high-frequency operation has been described. Using the nanoprober technique, MOS characteristics of failure bit in actual memory cells had been measured directly. It was confirmed that the drain current of a PMOS was about one order in magnitude smaller and the threshold voltage was about 1 V higher than that for normal bits.. A newly developed, unique selective etching technique using hydrazine mixture showed these degradations were caused by local gate depletion, and TEM observation showed the PMOS gate poly-Si of the failure bit had a huge grain. Minimizing grain size of the gate poly-Si is found to be quite effective for improving drain current degradation and suppressing this failure mode.
Scientific journal, English - Threshold voltage-related soft error degradation in a TFT SRAM cell
S Ikeda; Y Yoshida; S Kamohara; K Imato; K Ishibashi; K Takahashi
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 50, 2, 391-396, Feb. 2003, Peer-reviwed, This is the first report of abnormal behavior in the soft error rate (SER). dependence on supply voltage (Vcc) for a bottom-gated polysilicon PMOS thin-film transistor (TFT) static random access memory (SRAM). We found that the TFT SER does not continuously improve (as is expected and desirable) with increasing Vcc when We exceeds -Vth(threshold voltage) of the TFT within a range of about 0-2 K This was confirmed with samples of TFT with Vth intentionally varied from 0 to -5 V (by adjusting channel doping). A possible. explanation of this Vcc independence is proposed in the form of a SPICE simulation with as little as a 0.1-V TFT transient Vth shift due to the TFT's floating body. The accelerated SER was measured by using an Americium alpha particle source.
Scientific journal, English - A 9 mu W 50MHz 32b adder using a self-adjusted forward body bias in SoCs
K Ishibashi; T Yamashita; Y Arima; Minematsu, I; T Fujimoto
2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, IEEE, 46, 116-+, 2003, Peer-reviwed
International conference proceedings, English - Offset calibrating comparator array for 1.2-V, 6-bit, 4-gsample/s flash ADCs using 0.13-um generic CMOS technology
H Okada; Y Hashimoto; K Sakata; T Tsukada; K Ishibashi
ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, IEEE, Proceedings of the 29th Europe, 711-714, 2003, Peer-reviwed, A 1.2-V calibration comparator array for a Flash-type ADC has been developed using 0.13-mum generic CMOS technology. The developed offset calibration technique corrects the offset mismatch better than 6-bit resolution. By employing an offset calibration circuit in the comparator array, the comparator array can operate at low supply voltages. To evaluate the comparator array, a Obit Flash-type ADC was fabricated that occupies 0.198 mm.(2) With a 1.2-V power supply, it achieves 4.0 GSample/s and consumes 182 mW.
International conference proceedings, English - Low power SoC project in STARC
K Ishibashi; T Yamashita
2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, IEEE, 2003 International Symp. on VL, 180-183, 2003, Peer-reviwed, Low power SoC technology, which realizes ubiquitous computing era, is investigated. Low voltage operation of 0.5V for logic and memory IN and 1.0V operation for analog IP are target techniques. Such low voltage logic, memory and analog IPs are to be implemented in a single chip to realize super low power SoC.
International conference proceedings, English - A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit
M Yamaoka; K Yanagisawa; S Shukuri; K Norisue; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 37, 5, 599-604, May 2002, Peer-reviwed, A new memory redundancy technique using inverse-gate-electrode flash (ie-Flash) memory cells has been developed. The ie-Flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-Flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.
Scientific journal, English - A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias
M Miyazaki; G Ono; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 37, 2, 210-217, Feb. 2002, Peer-reviwed, In a speed-adaptive threshold-voltage CMOS (SA-V-t CMOS) scheme, the substrate bias is controlled so that delay in a circuit remains constant. The substrate bias is continuously changed from -1.5 V of reverse bias to 0.5 V of forward bias in order to compensate for fabrication-process fluctuation, supply-voltage variation, and operating-temperature variation. Advantages and disadvantages of substrate bias control with the forward bias are discussed. The SA-V-t CMOS scheme with forward bias is implemented in a 4.3M-transistor microprocessor. The controller occupies 320 x 400 mum in area and consumes 4-mA current. A 0.5-V forward bias raises the maximum operating frequency of the processor by 10%. The processor provides 400 VAX MIPS at 1.5-1.8 V supply with 320-380-mW power dissipation, that is, it achieves 1.2-GIPS/W performance.
Scientific journal, English - Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder
K Aisaka; T Aritsuka; S Misaka; K Toyama; K Uchiyama; K Ishibashi; H Kawaguchi; T Sakurai
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, IEEE, 2002 Symposium on VLSI Circuit, 216-217, 2002, Peer-reviwed, Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. ne authors first show through a mathematical analysis that FVC with only two frequency-voltage sets is sufficient for current low-Vdd CPU chips. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.
International conference proceedings, English - 0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme
M Yamaoka; K Osada; K Ishibashi
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, IEEE, 2002 Symposium on VLSI Circuit, 170-173, 2002, Peer-reviwed, We designed a logic library friendly SRAM array. The array uses rectangular-diffusion cell (RD-cell) and delta-boosted-array-voltage scheme (DBA-scheme). In the RD-cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA-scheme compensates it. Using the combination of RD-cell and DBA-scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency and 140-muW power dissipation and 0.9-muA standby current.
International conference proceedings, English - A V-driver circuit for lowering power of sub-0.1um bus
T Yamashita; Y Arima; K Ishibashi
2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, IEEE, 2002 Asia-Pacific ASIC, 267-270, 2002, Peer-reviwed, A bus driver circuit which reduces power dissipation of interconnect is described. The proposed V-driver prevents simultaneous signal transition of opposite direction. Simulated results show up to 42.2% power reduction for 65nm technology. Test chip was fabricated and measured result show 10.7% power reduction at 100MHz, 1.0V operation.
International conference proceedings, English - Universal-V-dd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
K Osada; JL Shin; M Khan; Y Liou; K Wang; K Shoji; K Kuroda; S Ikeda; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 36, 11, 1738-1744, Nov. 2001, Peer-reviwed, A universal-V-dd 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-mum enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.
Scientific journal, English - Universal-V-dd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
K Osada; JL Shin; M Khan; Y Liou; K Wang; K Shoji; K Kuroda; S Ikeda; K Ishibashi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 36, 11, 1738-1744, Nov. 2001, Peer-reviwed, A universal-V-dd 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-mum enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.
Scientific journal, English - CMOS process compatible ie-flash (inverse gate electrode flash) technology for system-on-a chip
S Shukuri; K Yanagisawa; K Ishibashi
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E84C, 6, 734-739, Jun. 2001, Peer-reviwed, A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability 5 V-programming with I ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 mum CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
Scientific journal, English - CMOS process compatible ie-flash (inverse gate electrode flash) technology for system-on-a chip
S Shukuri; K Yanagisawa; K Ishibashi
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E84C, 6, 734-739, Jun. 2001, Peer-reviwed, A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability 5 V-programming with I ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 mum CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
Scientific journal, English - CMOS process compatible ie-flash(inverse gate electrode flash) technology for system-on-a chip
S Shukuri; K Yanagisawa; K Ishibashi
PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, IEEE, 2001 IEEE Custom Integrated Ci, 179-182, 2001, Peer-reviwed, A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded In the common 0.14 mum CMOS process without any process modifications, has been developed The ie-flash cell consists of two elementary cells for OR-logical reading resulting in significant improvement of reliability. 5V-programming with 1ms duration and 1.2V-read operation of 35bit memory modules fabricated by a 0.14 mum CMOS process is demonstrated.
International conference proceedings, English - A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit
M Yamaoka; K Yanagisawa; S Shukuri; K Norisue; K Ishibashi
2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, JAPAN SOCIETY APPLIED ELECTROMAGNETICS & MECHANICS, 2001 Symposium on VLSI Circuit, 71-72, 2001, Peer-reviwed, A new memory redundancy technique using ie-Flash (inverse-gate-electrode flash) memory cells was developed. Ie-Flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic tester. This new redundancy technique was successfully implemented in the cache memories of a 32-bit RISC microprocessor.
International conference proceedings, English - Low Power Memory
K. Ishibashi
in the short course, 2001 SSDM(International Symposium on Solid-State Devices and Materials), in the short course, 2001 SSDM, 2001, Peer-reviwed
International conference proceedings, English - Substrate-Bias Techniques for SH4（未刊行論文）
K. Ishibashi
in the short course, 2001 VLSI Circuit Symposium, in the short course, 2001 VLSI, 2001, Peer-reviwed
International conference proceedings, English - 低電力システムクロック発生回路向け並列位相比較型ディレーロックドループ
宮崎祐行; 石橋孝一郎
電子情報通信学会論文誌Ｃ, Vol.J83-C, No.6, p.p. 502-508, 2000, Peer-reviwed
Scientific journal, Japanese - A 2-ns-access, 285-MHz, two-port cache macro using double global bit-line pairs
K Osada; H Higuchi; K Ishibashi; N Hashimoto; K Shiozawa
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E83C, 1, 109-114, Jan. 2000, Peer-reviwed, We fabricated a 16-kB cache macro using 0.35-mu m quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512 x 256 b) cache macro that has a 2-ns access time. This high-speed performance is enabled by a hierarchical bit-line architecture: that uses double global bit-line pairs (WGBs); and a high-speed timing-insensitive sense amplifier (ISA) that shortens the access time.
Scientific journal, English - A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias
M. Miyazaki; G. Ono; T. Hattori; K. Shiozawa; K. Uchiyama; K. Ishibashi
2000 IEEE International Solid-State Circuits Conference, 2000 IEEE International Solid-, 2000, Peer-reviwed
International conference proceedings, English - Quantitative Study of SA-Vt CMOS Scheme Based on the Evaluation of Device Fluctuation
G. Ono; M. Miyazaki; K. Ishibashi
2000 International Conference on Solid State Devices and Materials, 2000 International Conference, 2000, Peer-reviwed
International conference proceedings, English - An 18-mu A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
H Mizuno; K Ishibashi; T Shimura; T Hattori; S Narita; K Shiozawa; S Ikeda; K Uchiyama
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 34, 11, 1492-1500, Nov. 1999, Peer-reviwed, A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-mu m, five-metal, dual-oxide-thickness, CMOS technology and two power-down modes (i.e., a standby mode and a data-retention mode), The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-mu A standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode, This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or pn junction current. The current consumption is only 17.8 mu A when operating off a 1-V supply in the data-retention mode.
Scientific journal, English - An 18-mu A standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
H Mizuno; K Ishibashi; T Shimura; T Hattori; S Narita; K Shiozawa; S Ikeda; K Uchiyama
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 34, 11, 1492-1500, Nov. 1999, Peer-reviwed, A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-mu m, five-metal, dual-oxide-thickness, CMOS technology and two power-down modes (i.e., a standby mode and a data-retention mode), The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-mu A standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode, This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or pn junction current. The current consumption is only 17.8 mu A when operating off a 1-V supply in the data-retention mode.
Scientific journal, English - A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio
H Mizuno; K Ishibashi
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 7, 1, 139-144, Mar. 1999, Peer-reviwed, This paper describes an on-chip cache, called a separated bit-line unified cache, which minimizes the chip-area cost in highperformance microprocessors. This unified cache has two ports; one for the instruction bus and the other for the data bus. A separated bit-line memory hierarchy architecture realizes memory hierarchy design with only 10%-20% area overhead. The total cache area can be reduced by more than 20%-30% on the average at capacities of larger than 64 KB with the same hit rate as the conventional cache. The cache latency reaches 4.2 ns at a supply voltage of 1 V, Additionally, the cache is physically addressable even if the cache has a large capacity.
Scientific journal, English - Analog circuit design methodology in a low power RISC microprocessor
Koichiro Ishibashi; Hisayuki Higuchi; Toshinobu Shimbo; Kunio Uchiyama; Kenji Shiozawa; Naotaka Hashimoto; Shuji Ikeda
Analog Integrated Circuits and Signal Processing, 20, 2, 85-94, 1999, Peer-reviwed, There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm2 test chip with the super H architecture using 0.35-μm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.
Scientific journal, English - A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems
M. Miyazaki; K. Ishibashi
AP-ASIC '99. The First IEEE Asia Pacific Conference, AP-ASIC '99. The First IEEE As, 1999, Peer-reviwed
International conference proceedings, English - Analog circuit design methodology in a low power RISC microprocessor
K Ishibashi; H Higuchi; T Shimbo; K Uchiyama; K Shiozawa; N Hashimoto; S Ikeda
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E81A, 2, 210-217, Feb. 1998, There are various kinds of analog CMOS circuits in microprocessors. IOs. clock distribution circuits including PLL. memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased bq using a CAM I with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit. enabling single-cycle operation. A fabricated 96-mm(2) test chip with the super H architecture using 0.35-mu m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.
Scientific journal, English - A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit
O. Nishii; F. Arakawa; K. Ishibashi; S. Nakano; T. Shimura; K. Suzuki; M. Tachibana; Totsuka; T. Tsunoda; K. Uchiyama; T. Yamada; T. Hattori; H. Maejima; N. Nakagawa; S. Narita; M. Seki; Y. Shimazaki; R. Satomura; T. Takasuga; A. Hasegawa
1998 IEEE International Solid-state Circuits Conference, 1998 IEEE International Solid-, 1998, Peer-reviwed
International conference proceedings, English - A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
H. Mizuno; K. Ishibashi
1998 IEEE International Solid-state Circuits Conference, 1998 IEEE International Solid-, 1998, Peer-reviwed
International conference proceedings, English - A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs
M Miyazaki; H Mizuno; K Ishibashi
1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, ASSOC COMPUTING MACHINERY, 1998 International Symposium o, 48-53, 1998, Peer-reviwed, In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25-mu m CMOS devices as a test circuit, we found that the worst-case operating frequency was improved from 20 MHz to 55 MHz, and the fluctuation of the operating frequency was suppressed from 44 % to 15 % while the supply-voltage variation was under 0.1 V with a 1.8 V supply voltage.
International conference proceedings, English - A 6.93-mu m(2) full CMOS SRAM cell technology for 1.8-V high-performance cache memory
M Minami; N Ohki; H Ishida; T Yamanaka; A Shimizu; K Ishibashi; A Satoh; T Kure; T Nishida; T Nagano
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E80C, 4, 590-596, Apr. 1997, Peer-reviwed, A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-mu m spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-mu m n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-mu m p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-mu m CMOS process technology. A 6.93-mu m(2) and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.
Scientific journal, English - The design of 300MIPS microprocessor with a full associative TLB for hand-held PC OS
K Ishibashi; H Higuchi; Y Shimbo; F Arakawa; O Nishii; N Nakagawa; H Maejima; K Osada; K Norisue; R Satomura; Aoki; Y Shimazaki; K Tanaka; T Hattori; K Shiozawa; K Kudo; K Uchiyama; S Narita; J Nishimoto; T Nagano; S Ikeda; K Kuroda; T Takeda; N Hashimoto
1997 SYMPOSIUM ON VLSI CIRCUITS, JAPAN SOCIETY APPLIED PHYSICS, 1997 Symposium on VLSI Cirvuit, 9-10, 1997, Peer-reviwed
International conference proceedings, English - A lean-power gigascale LSI using hierarchical V-BB routing scheme with frequency adaptive V-T CMOS
H Mizuno; M Miyazaki; K Ishibashi; Y Nakagome; T Nagano
1997 SYMPOSIUM ON VLSI CIRCUITS, JAPAN SOCIETY APPLIED PHYSICS, 1997 IEEE International Solid-, 95-96, 1997, Peer-reviwed
International conference proceedings, English - A lean-power gigascale LSI using hierarchical V-BB routing scheme with frequency adaptive V-T CMOS
H Mizuno; M Miyazaki; K Ishibashi; Y Nakagome; T Nagano
1997 SYMPOSIUM ON VLSI CIRCUITS, JAPAN SOCIETY APPLIED PHYSICS, 1997 Symposium on VLSI Circuit, 95-96, 1997, Peer-reviwed
International conference proceedings, English - An 8-mW, 8-kB cache memory using an automatic-power-save architecture for low power RISC microprocessors
Y Shimazaki; K Norisue; K Ishibashi; H Maejima
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E79C, 12, 1693-1698, Dec. 1996, Peer-reviwed, An embedded cache memory for low power RISC microprocessors is described. An automatic-power-save architecture (APSA) enables the cache memory to operate with high speed at high frequencies, and with low power dissipation at low frequencies. A pulsed word technique (PWT) and an isolated bit line technique (IBLT) reduce the power dissipation of the cache memory effectively. Using these three techniques, the power dissipation of the cache memory is reduced to almost 60% of the conventional cache memory at 60 MHz and to 20% at a clock frequency of 10 MHz. An 8 KByte test chip using 0.5 mu m CMOS technology was fabricated, and it achieves 80 MHz operation at a supply voltage of 3.1 V, and 8 mW operation at a supply voltage of 2.5 V at 10 MHz.
Scientific journal, English - A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators
H Mizuno; N Matsuzaki; K Osada; T Shinbo; N Ohki; H Ishida; K Ishibashi; T Kure
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 31, 11, 1618-1624, Nov. 1996, Peer-reviwed, A l-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-mu m CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V, This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons.
Scientific journal, English - A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators
H Mizuno; N Matsuzaki; K Osada; T Shinbo; N Ohki; H Ishida; K Ishibashi; T Kure
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 31, 11, 1618-1624, Nov. 1996, Peer-reviwed, A l-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-mu m CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V, This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons.
Scientific journal, English - High-speed CMOS SRAM technologies for cache applications
K Ishibashi
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E79C, 6, 724-734, Jun. 1996, This paper describes high-speed CMOS SRAM circuit technologies used in cache memories. In recent years, high-speed SRAM technology has led to higher cycle frequencies, brit the rate of increase in the SRAM density has slowed. Operating modes of high-speed SRAMs are compared and the advantage of wave-pipelined SRAMs in terms of cycle frequency is shown. Three types of sense amplifiers used in SRAMs are also compared from the viewpoint of speed and power dissipation. Current sense amplifiers provide high-speed operation with low power dissipation, while latch-type sense amplifiers appear most suitable for ultra-low-power SRAMs. Low voltage operation and size reduction of full CMOS cells are now the most pressing issues in the development of SRAMs for cache memories.
Scientific journal, English - A cost-oriented two-port unified cache for low-power RISC microprocessors
H Mizuno; K Ishibashi
1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, I E E E, 1996 Symposium on VLSI Circuit, 72-73, 1996, Peer-reviwed
International conference proceedings, English - ADVANCED TFT SRAM CELL TECHNOLOGY USING A PHASE-SHIFT LITHOGRAPHY
T YAMANAKA; T HASHIMOTO; N HASEGAWA; T TANAKA; N HASHIMOTO; A SHIMIZU; N OHKI; K ISHIBASHI; K SASAKI; T NISHIDA; T MINE; E TAKEDA; T NAGANO
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 42, 7, 1305-1313, Jul. 1995, Peer-reviwed, An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells, The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 mu m to be made using the conventional stepper, Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor, Despite the small cell-ratio, stable operation Is assured by using advanced polysilicon PMOS TFT's for load devices, The effect of the Si3N4 multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated, To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated, A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6 x 10(6) are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns.
Scientific journal, English - A 6-NS 4-MB CMOS SRAM WITH OFFSET-VOLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS
K ISHIBASHI; K TAKASUGI; K KOMIYAJI; H TOYOSHIMA; T YAMANAKA; A FUKAMI; N HASHIMOTO; N OHKI; A SHIMIZU; T HASHIMOTO; T NAGANO; T NISHIDA
IEICE TRANSACTIONS ON ELECTRONICS, IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, E78C, 6, 728-734, Jun. 1995, Peer-reviwed, A 4-Mb CMOS SRAM with 3.84 mu m(2) TFT load cells is fabricated using 0.25-mu m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.
Scientific journal, English - A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro Ishibashi; Kunihiro Komiyaji; Toshiaki Yamanaka; Akira Fukami; Takahiro Nagano
IEEE Journal of Solid-State Circuits, 30, 4, 480-486, 1995, Peer-reviwed, A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells. © 1995 IEEE
Scientific journal, English - A 300MHZ 4-MB WAVE-PIPELINE CMOS SRAM USING A MULTI-PHASE PLL
K ISHIBASHI; K KOMIYAJI; H TOYOSHIMA; M MINAMI; N OOKI; H ISHIDA; T YAMANAKA; T NAGANO; T NISHIDA
1995 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, I E E E, 38, 308-309, 1995, Peer-reviwed
International conference proceedings, English - A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
S Narita; K Ishibashi; S Tachibana; K Norisue; Y Shimazaki; J Nishimoto; K Uchiyama; T Nakazawa; K Hirose; Kudoh, I; R Izawa; S Matsui; S Yoshioka; M Yamamoto; Kawasaki, I
1995 SYMPOSIUM ON VLSI CIRCUITS, JAPAN SOC APPLIED PHYSICS, 1995 Symposium on VLSI Circuit, 59-60, 1995, Peer-reviwed
International conference proceedings, English - An automatic-power-save cache memory for low-power RISC processors
Y. Shimazaki; K. Ishibashi; K. Norisue; S. Narita; K. Uchiyama; T. Nakazawa; I. Kudoh; R. Izawa; S. Yoshioka; S. Tamaki; S. Nagata; I. Kawasaki; K. Kuroda
IEEE Symposium on Low Power Electronics and Design 1995, IEEE Symposium on Low Power El, 1995, Peer-reviwed
International conference proceedings, English - A 6.93-mu m(2) n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
M Minami; N Ohki; H Ishida; T Yamanaka; K Ishibashi; A Shimizu; T Kure; T Nishida; T Nagano
1995 SYMPOSIUM ON VLSI TECHNOLOGY, I E E E, 1995 Symposium on VLSI Technol, 13-14, 1995, Peer-reviwed
International conference proceedings, English - A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers
Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Koichi Motohashi; Toshiro Aoto; Kyoichiro Asayama; Atsuyosi Koike; Fumio Kojima; Haruhito Iida; Katsuro Sasaki
IEEE Journal of Solid-State Circuits, 29, 4, 411-418, 1994, Peer-reviwed, A 16-Mb CMOS SRAM using 0.4-µm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved. © 1994 IEEE
Scientific journal, English - A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs
Shuji Ikeda; Kyoichiro Asayama; Naotaka Hashimoto; Eri Fujita; Yasuko Yoshida; Atsuyosi Koike; Toshiaki Yamanaka; Koichiro Ishibashi; Satoshi Meguro
IEDM Tech. Dig., pp. 809-812, Dec. 1993, Peer-reviwed
Scientific journal, English - A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs
Shuji Ikeda; Kyoichiro Asayama; Naotaka Hashimoto; Eri Fujita; Yasuko Yoshida; Atsuyosi Koike; Toshiaki Yamanaka; Koichiro Ishibashi; Satoshi Meguro
IEDM Tech. Dig., IEDM Tech. Dig., Dec. 1993, Peer-reviwed
International conference proceedings, English - A 12.5NS 16MB CMOS SRAM
K ISHIBASHI; K KOMIYAJI; S MORITA; T AOTO; S IKEDA; K ASAYAMA; A KOIKE; T YAMANAKA; N HASHIMOTO; H IIDA; F KOJIMA; K MOTOHASHI; K SASAKI
1993 SYMPOSIUM ON VLSI CIRCUITS, JAPAN SOC APPLIED PHYSICS, 1993 Symposium on VLSI Circuit, 103-104, 1993, Peer-reviwed
International conference proceedings, English - A 1-V TFT-LOAD SRAM USING A 2-STEP WORD-VOLTAGE METHOD
K ISHIBASHI; K TAKASUGI; T YAMANAKA; T HASHIMOTO; K SASAKI
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 27, 11, 1519-1524, Nov. 1992, Peer-reviwed, A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFET's. An access time of 250 ns and a standby current of 0.23 muA were achieved for a 4-kb test chip using a 10.2-mum2 TFT-load cell. This technology is applicable for high-density and single-battery operational SRAM's.
Scientific journal, English - A 7-NS 140-MW 1-MB CMOS SRAM WITH CURRENT SENSE AMPLIFIER
K SASAKI; K ISHIBASHI; K UEDA; K KOMIYAJI; T YAMANAKA; N HASHIMOTO; H TOYOSHIMA; F KOJIMA; A SHIMIZU
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 27, 11, 1511-1518, Nov. 1992, Peer-reviwed, A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and a pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-mum2 high-density memory cell uses a new parallel transistor layout and phase-shifting photo-lithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-mum CMOS quadruple-poly and double-metal technology. The chip measures 3.96 mm x 7.4 mm (29 mm2).
Scientific journal, English - A VOLTAGE DOWN CONVERTER WITH SUBMICROAMPERE STANDBY CURRENT FOR LOW-POWER STATIC RAMS
K ISHIBASHI; K SASAKI; H TOYOSHIMA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 27, 6, 920-926, Jun. 1992, Peer-reviwed, A submicroampere standby current voltage down converter (VDC) for high-density, low-power static RAM's is described. The current consumption of the VDC in standby mode can be decreased by using a new low-current and temperature-independent current source circuit. The total current is less than 0.5-mu-A at external voltage ranging from 3 to 5 V and at temperatures ranging from -20 to 80-degrees-C. The voltage-follower circuits for standby and operation modes are stable despite the low current consumption in the standby mode. The phase margin of the voltage follower for standby mode is 50-degrees and that for operation mode is 90-degrees. This indicates that the VDC is a promising circuit for battery-backup and high-density static RAM's.
Scientific journal, English - A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
Koichiro Ishibashi; Katsuro Sasaki; Toshiaki Yamanaka; Hiroshi Toyoshima; Fumio Kojima
IEEE Journal of Solid-State Circuits, 27, 4, 674-677, 1992, Peer-reviwed, An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of —3.6 V. © 1992 IEEE
Scientific journal, English - Low power, low voltage memories for portable electronics
O. Minato; K. Ishibashi
1991 International Symposium on Technology, Systems and Applications, 1991 International Symposium o, 1991, Peer-reviwed
International conference proceedings, English - A 23-NS 4-MB CMOS SRAM WITH 0.2-MU A STANDBY CURRENT
K SASAKI; K ISHIBASHI; K SHIMOHIGASHI; T YAMANAKA; N MORIWAKI; S HONJO; S IKEDA; A KOIKE; S MEGURO; O MINATO
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 25, 5, 1075-1081, Oct. 1990, Peer-reviwed
Scientific journal, English - An a-Immune, 2-V Supply Voltage SRAM Using a Polysilicon PMOS Load Cell
Koichiro Ishibashi; Toshiaki Yamanaka; Katsuhiro Shimohigashi
IEEE Journal of Solid-State Circuits, 25, 1, 55-60, 1990, Peer-reviwed, - A SRAM for a supply voltage of as low as 2 V is investigated for realizing high-density SRAM’s using deep submicrometer devices. The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured. © 1990 IEEE
Scientific journal, English - A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography
T. Yamanaka; N. Hasegawa; T. Tanaka; K. Ishibashi; T. Hashimoto; A. Shimizu; N. Hashimoto; K. Sasaki; T. Nishida; E. Takeda
1990 International Electron Devices Meeting, 1990 International Electron De, 1990, Peer-reviwed
International conference proceedings, English - A 9-NS 1-MBIT CMOS SRAM
K SASAKI; K ISHIBASHI; T YAMANAKA; N HASHIMOTO; T NISHIDA; K SHIMOHIGASHI; S HANAMURA; S HONJO
IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 24, 5, 1219-1225, Oct. 1989, Peer-reviwed
Scientific journal, English - A 25 μm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity
T. Yamanaka; T. Hashimoto; N. Hashimoto; T. Nishida; A. Shimuzu; K. Ishibashi; Y. Sakai; K. Shimohigashi; E. Takeda
Electron Devices Meeting., Technical Digest., International, Electron Devices Meeting., Tec, 1988, Peer-reviwed
International conference proceedings, English - A 42ns 1Mb CMOS SRAM
O. Minato; T. Sasaki; S. Honjo; K. Ishibashi; Y. Sasaki; N. Moriwaki; K. Nishimura; Y. Sakai; S. Meguro; M. Tsunematsu; T. Masuhara
1987 IEEE International Solid-state Circuits Conference, 1987 IEEE International Solid-, 1987, Peer-reviwed
International conference proceedings, English - SPE-COSI2 SUBMICROMETER LINES BY LIFT-OFF USING SELECTIVE REACTION AND ITS APPLICATION TO A PERMEABLE-BASE TRANSISTOR
K ISHIBASHI; S FURUKAWA
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 33, 3, 322-327, Mar. 1986, Peer-reviwed
Scientific journal, English - FORMATION OF UNIFORM SOLID-PHASE EPITAXIAL COSI2 FILMS BY PATTERNING METHOD
K ISHIBASHI; S FURUKAWA
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, JAPAN J APPLIED PHYSICS, 24, 8, 912-917, 1985, Peer-reviwed
Scientific journal, English - Si permeable base transistor by metal/semiconductor hetero-epitaxy
K. Ishibashi; S. Furukawa
1984 International Electron Devices Meeting, 1984 International Electron De, 1984, Peer-reviwed
International conference proceedings, English - Formation of SPE-CoSi2 Submicron Line by Lift Off Using Selective Reaction
K. Ishibashi; S. Furukawa
1984 Internaitonal Conference on Solid-state Devices and Materials, 1984 Internaitonal Conference, 1984, Peer-reviwed
International conference proceedings, English - STUDY OF THE UNIFORMITY AND STOICHIOMETRY OF COSI2 FILMS USING RUTHERFORD BACKSCATTERING SPECTROSCOPY AND SCANNING ELECTRON-MICROSCOPY
K ISHIBASHI; S FURUKAWA
APPLIED PHYSICS LETTERS, AMER INST PHYSICS, 43, 7, 660-662, 1983, Peer-reviwed
Scientific journal, English - Study on Formation of Solid-Phase-Epitaxial CoSi2 Films and Patterning Effects
K. Ishibashi; H. Ishiwara; S. Furukawa
1983 International Conference on Solid-state Devices and Materials, 1983 International Conference, 1983, Peer-reviwed
International conference proceedings, English
MISC
- 急峻なSSを持つ"PN-Body Tied SOI-FET"のCMOSインバータ伝達特性
イシグロ ショウタ; イダ ジロウ; モリ タカユキ; イシバシ コウイチロウ
映像情報メディア学会, Aug. 2020, 映像情報メディア学会技術報告 = ITE technical report, 44, 17, 57-60, Japanese, 1342-6893, 40022323689, AN1059086X - 急峻なSSを持つ"PN Body-Tied SOI-FET"におけるBOX中の正電荷と基板バイアスの影響
ヤブキ ワタル; イダ ジロウ; モリ タカユキ; イシバシ コウイチロウ; アライ ヤスオ
電子情報通信学会, Aug. 2019, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 119, 162, 89-93, Japanese, 0913-5685, 40021997138, AA1123312X - 極急峻SSを持つ"PN-Body Tied SOI-FET"を使った極低電力レクテナ
ヤマダ タクヤ; イダ ジロウ; モリ タカユキ; ヤスマル ノブヒコ; イトウ ケンジ; イシバシ コウイチロウ
電子情報通信学会, Aug. 2019, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 119, 161, 95-98, Japanese, 0913-5685, 40021997414, AA1123312X - 招待講演 急峻なSSを持つPN-Body Tied SOI-FETを用いたMOS Diode接続での特性および微小電圧整流実験
モモセ シュン; イダ ジロウ; ヤマダ タクヤ; モリ タカユキ; イトウ ケンジ; イシバシ コウイチロウ; アライ ヤスオ
電子情報通信学会, Nov. 2018, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 118, 291, 59-64, Japanese, 0913-5685, 40021747494, AA1123312X - 急峻なSSを持つ"PN-Body Tied SOI-FET"を使った極低電圧整流実験
モモセ シュン; イダ ジロウ; ヤマダ タクヤ; モリ タカユキ; イトウ ケンジ; イシバシ コウイチロウ; アライ ヤスオ
電子情報通信学会, Aug. 2018, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 118, 173, 31-34, Japanese, 0913-5685, 40021657845, AA1123312X - B-18-32 Low-power synchronous communication system in the intermittent operation sensor network system
Ishigaki Shohei; Ishibashi Koichiro
The Institute of Electronics, Information and Communication Engineers, 01 Mar. 2016, Proceedings of the IEICE General Conference, 2016, 2, 530-530, Japanese, 110010038411, AN10471452 - A-1-6 Low Power Operations of Sensor Network Systems by Router Intermittent Operations
Morohashi Shotaro; Ishibashi Koichiro; Tokoi Yoshiyuki; Iramina Chisato
The Institute of Electronics, Information and Communication Engineers, 24 Feb. 2015, Proceedings of the IEICE General Conference, 2015, 6-6, Japanese, 110009943757, AN10471452 - C-10-9 Characteristics of comb type MEMS resonator and stored energy
Nagamura Shinya; Ishige Tsuyoshi; Ishibashi Koichiro
The Institute of Electronics, Information and Communication Engineers, 24 Feb. 2015, Proceedings of the IEICE General Conference, 2015, 2, 56-56, Japanese, 110009926950, AN10471452 - Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation
Makiyama H.; Yamamoto Y.; Oda H.; Kamohara S.; Sugii N.; Yamaguchi Y.; Ishibashi K.; Mizutani T.; Hiramoto T.
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (V_- ). In the ultralow-V_
- regime, however, the upsurging delay (τ_
) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at V_ - = 0.4 V., The Institute of Electronics, Information and Communication Engineers, 16 Oct. 2014, Technical report of IEICE. SDM, 114, 255, 61-68, Japanese, 0913-5685, 110009959306, AN10013254
- ). In the ultralow-V_
- Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4V) Operation
Makiyama H.; Yamamoto Y.; Shinohara H.; Iwamatsu T.; Oda H.; Sugii N.; Ishibashi K.; Mizutani T.; Hiramoto T.; Yamaguchi Y.
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (V_- ). In the ultralow-V_
- regime, however, the upsurging delay (τ_
) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at V_ - = 0.4 V., The Institute of Electronics, Information and Communication Engineers, 29 Jan. 2014, Technical report of IEICE. SDM, 113, 420, 35-38, Japanese, 0913-5685, 110009825264, AN10013254
- ). In the ultralow-V_
- CT-2-1 Trend in Low Voltage and Low Power Technologies
Ishibashi Koichiro
The Institute of Electronics, Information and Communication Engineers, 28 Aug. 2012, Proceedings of the Society Conference of IEICE, 2012, 2, "SS-12", Japanese, 110009593932, AN10489017 - A Fast-Transient-Response Digital Low-Dropout Regulator Comprising Thin-Oxide MOS Transistors in 40-nm CMOS process
ONOUCHI Masafumi; OTSUGA Kazuo; IGARASHI Yasuto; IKEYA Toyohito; MORITA Sadayuki; ISHIBASHI Koichiro; YANAGISAWA Kazumasa
A digital low-dropout (LDO) regulator comprising only thin-oxide MOS transistors was developed. The input voltage to the LDO is set to be higher than the nominal overdrive voltage of thin-oxide MOS transistors by applying the proposed overdrive-voltage relaxation scheme. In the LDO, fast transient response can be achieved by applying an output capacitor-less design, which is based on power-MOS features as follows: 1-GHz switching and the small number of levels whereas a wide range of load current (400μA-250mA) can be covered by applying the proposed power-MOS configuration. The LDO occupies only 0.057mm^2 area using 40-nm CMOS technology, and the measured the transient response time is only 0.07μs., The Institute of Electronics, Information and Communication Engineers, 26 Jul. 2012, Technical report of IEICE. SDM, 112, 169, 105-110, Japanese, 0913-5685, 110009627093, AN10013254 - Low Power Technologies and Scaling Law Toward Future
ISHIBASHI Koichiro
LSI density has been increasing by Moore's law, and performance of LSI has also been increasing with decreasing power dissipation. Many low power techniques have been developed, and LSI power has been drastically decreased by scaling law. The low power nature of LSI has exploited many applications and has created ITC society. However, recent trend of saturated power supply voltage reduction rate due to variability and leakage of advanced MOS transistors will make issues of power consumption again. Multi CPU core architecture is the one of solution for the issue, but there will be a limitation of the number of core operating at the same time in the future. We need further to reduce the power supply voltage again to around 0.4V with new device structure such as FINFET or SOTB., The Institute of Electronics, Information and Communication Engineers, 12 Jan. 2012, Technical report of IEICE. ICD, 111, 388, 21-22, Japanese, 110009481167, AN10013276 - On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors
KIM Jinmyoung; NAKURA Toru; TAKATA Hidehiro; ISHIBASHI Koichiro; IKEDA Makoto; ASADA Kunihiro
This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18μm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement., The Institute of Electronics, Information and Communication Engineers, 14 Jul. 2011, IEICE technical report, 111, 151, 69-72, Japanese, 0913-5685, 110008800873, AN10013276 - On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores Utilizing Parasitic Capacitance of Sleep Blocks
KIM Jinmyoung; NAKURA Toru; TAKATA Hidehiro; ISHIBASHI Koichiro; IKEDA Makoto; ASADA Kunihiro
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitance of sleep blocks. It has smaller area penalty than conventional on-chip large MOS capacitors because we use parasitic capacitance of sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18μm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast power mode transition possible for dynamic voltage scaling and power gating., The Institute of Electronics, Information and Communication Engineers, 19 Aug. 2010, IEICE technical report, 110, 182, 1-4, Japanese, 0913-5685, 110008094989, AN10013254 - A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control
ONOUCHI Masafumi; KANNO Yusuke; SAEN Makoto; KOMATSU Shigenobu; YASU Yoshihiko; ISHIBASHI Koichiro
A "wide-range voltage-and-frequency clock synchronizer" for maintaining synchronization during voltage-scaling transition in dynamic voltage-and-frequency scaling (DVFS) was developed. The key feature of the synchronizer is so-called predictive-delay-adjustment scheme based on a relative skew measure. The scheme reduces the area of the WRCS by 77%. The area of the fabricated WRCS in a 40-nm CMOS is only 5.65×10^<-3>mm^2. It was demonstrated for the first time that measured skew is suppressed to less than 6.8% of clock period in the case of wide-range voltage variation (0.8-1.55 V) and wide frequency range (100 MHz - 1 GHz). Moreover, current dissipation of the synchronizer is only 0.48 mA at 1.1-V 100-MHz operation., The Institute of Electronics, Information and Communication Engineers, 12 May 2010, IEICE technical report, 110, 36, 67-72, Japanese, 0913-5685, 110008001513, AN10013323 - A 65nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die
OHBAYASHI Shigeki; YABUUCHI Makoto; KONO Kazushi; ODA Yuji; IMAOKA Susumu; USUI Keiichi; YONEZU Toshiaki; IWAMOTO Takeshi; NII Koji; TSUKAMOTO Yasumasa; ARAKAWA Masashi; UCHIDA Takahiro; MAKINO Hiroshi; ISHIBASHI Koichiro; SHINOHARA Hirofumi
We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair scheme for an embedded 6T-SRAM to achieve a KGD-SoC. We febricated a 16M-SRAM with these techniques using 65 nm LSTP technology, and confirmed its efficient operation. The WLBI mode has almost no area penalyy and a speed penalty of only 50 ps. The leak-bit redundancy area penalty is less than 2%., The Institute of Electronics, Information and Communication Engineers, 05 Apr. 2007, IEICE technical report, 107, 1, 59-64, English, 0913-5685, 110006272865, AN10013276 - Low Power SOC Design using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for sub-100-nm LSTP technology
OZAWA Osamu; FUKUOKA Kazuki; IGARASHI Yasuto; KURAISHI Takashi; YASU Yosihiko; MAKI Yukio; IPPOSHI Takashi; OCHIAI Toshihiko; SHIRAHATA Masayoshi; ISHIBASHI Koichiro
The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 26-32%. A level shifter (LF) and Data-Retention-FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of an SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively., The Institute of Electronics, Information and Communication Engineers, 07 Dec. 2006, IEICE technical report, 106, 425, 115-119, Japanese, 0913-5685, 110006163156, AN10013276 - Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability
TSUKAMOTO Yasumasa; NII Koji; IMAOKA Susumu; ODA Yuji; OHBAYASHI Shigeki; YABUUCHI Makoto; MAKINO Hiroshi; ISHIBASHI Koichiro; SHINOHARA Hirofumi
The 6T-SRAM cells in the sub-100nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ_). In this paper, to achieve high-yield SRAM array in presence of random σ_ component, we propose a worst-case analysis that determines the boundary of the stable Vth region for SRAM read/write DC margin (Vth Curve). Applying this method to our original 65nm SPICE model, we show some characteristic behavior of the Vth Curve. Throughout this paper, we suggest new criteria to discuss SRAM array stability with Vth variability., The Institute of Electronics, Information and Communication Engineers, 06 Apr. 2006, IEICE technical report, 106, 2, 95-100, English, 0913-5685, 110004718934, AN10013276 - Switch transistor techniques for both low standby power and low power operation
YAMASHITA Takahiro; FUJIMOTO Tetsuya; ISHIBASHI Koichiro
Switch transistor techniques for both low power operation and low standby power has been described. 16bit multipliers are used for an example. The power switch consists of small sized transistor and intermediate-sized controllable-gate transistor. The switch allows raised virtual ground (VGND) for ground bounce, which reduces operating power. Test chip was fabricated using 0.13um CMOS technology Measured results proved 36.0% power reduction of 16bit multiplier at 50MHz operation., The Institute of Electronics, Information and Communication Engineers, 13 Aug. 2004, Technical report of IEICE. SDM, 104, 249, 7-12, Japanese, 0913-5685, 110003311155, AN10013254 - 増大するプロセッサの消費電力(1) - 省電力化のセオリーとは
石橋孝一郎
Apr. 2003, Web 雑誌 マイコミジャーナル, 2003/4/4, Japanese, Introduction other - 増大するプロセッサの消費電力(2) - 基板バイアス技術を採用
石橋孝一郎
Apr. 2003, Web 雑誌 マイコミジャーナル, 2003/4/4, Japanese, Introduction other - 0.4-V SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme
YAMAOKA Masanao; OSADA Kenichi; ISHIBASHI Koichiro
We designed a 0.4-V operating SRAM array. The array uses rectangular-diffusion cell (RD-cell) and delta-boosted-array-voltage scheme (DBA-scheme). In the RD-cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA-scheme compensates it. Using the combination of RD-cell and DBA-scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency and 140-μW power dissipation and 0.9-μA standby current., The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. ICD, 102, 274, 59-64, Japanese, 0913-5685, 110003494090, AN10013276 - 0.4-V SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme
YAMAOKA Masanao; OSADA Kenichi; ISHIBASHI Koichiro
We designed a 0.4-V operating SRAM array. The array uses rectangular-diffusion cell (RD-cell) and delta-boosted-array-voltage scheme (DBA-scheme). In the RD-cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA-scheme compensates it. Using the combination of RD-cell and DBA-scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency and 140-μW power dissipation and 0.9-μA standby current., The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. SDM, 102, 272, 59-64, Japanese, 0913-5685, 110003494056, AN10013254 - What is the most suitable on-chip memory for 90-65nm CMOS technology
ISHIBASHI Koichiro; KAWASHIMA Shoichiro; HIRAKI Mitsuru; NAKASE Yasunobu; ISHII Tomoyuki; SUGIBAYASHI Naohiko; MIYANO Shinji
It is predicted that on -chip memory would dominate chips as technology is advanced. SoC can afford to contain high-density on-chip memory then, resulting in high performance and low power consumption of the system. The advanced technology needs fine structure as well as low voltage operation, so the on-chip memory that is well adapted to the technology is necessary. Specialists of various kinds of on-chip memories will discuss merits and demerits of their memories for 90 to 65 -nm CMOS technology., The Institute of Electronics, Information and Communication Engineers, 05 Apr. 2002, Technical report of IEICE. ICD, 102, 3, 39-42, Japanese, 0913-5685, 110004024908, AN10013276
Books and other publications
- 環境発電ハンドブック第2版 第4章電磁波発電と無線電力伝送 1環境電波からのエネルギーハーべスティング技術
石橋孝一郎; Nguyen Thuy Linh
Japanese, Joint work, 第4章電磁波発電と無線電力伝送, ㈱エヌ・ティー・エス, 29 Oct. 2021 - Energy Harvesting Handbook, 2nd Edition
Koichiro Ishibashi; Nguyen Thuy Linh
Scholarly book, Japanese, Contributor, 第４章電磁波発電と無線電力伝送, NTS, 29 Oct. 2021 - 環境発電ハンドブック 第2版
石橋孝一郎; Nguyen Thuy Linh
Scholarly book, Japanese, Joint work, 第4章 電磁波発電と無線電力伝送（マイクロ波とワイヤレス給電）, 株式会社エヌ・ティー・エス, 29 Oct. 2021 - Low Power and Reliable SRAM Memory Cell and Cell Array Design
Koichiro Ishibashi; Kenichi Osada; Masanao Yamaoka; Eishi Ibe; Koji Nii; Tsukamoto Yasumasa
English, Editor, Springer Science + Business Media, Oct. 2011 - ＳＲＡＭの低電力化技術
石橋孝一郎
Japanese, Joint work, 低消費電力、高速ＬＳＩ技術(桜井貴康編集委員長の第２章), リアライズ社, 1998 - Layered Structures and Interface Kinetics:Their Technology and Applications
Koichiro Ishibashi; Seijiro Furukawa
English, Joint work, Formation of Smooth CoSi2 films by Solid Phase Epitaxy, KTK Scientific Publishers/Tokyo, D. Reidel Publishing Company/Dordrechit, Boston, London, 1985
Lectures, oral presentations, etc.
- Bacteria Classification by small scale Deep Learning
Koichiro Ishibashi
Invited oral presentation, English, NICS 2022, Invited, ホーチミン, International conference
31 Oct. 2022 - Low power Wake up Receiver for IoT
Koichiro Ishibashi
Invited oral presentation, English, ICICDT 2022, Invited, ハノイ, International conference
24 Sep. 2022 - RFエネルギーハーベスティング技術とIOT応用の新展開
Invited oral presentation, Japanese, 応用物理学会 2022, Invited, 東北大学, Domestic conference
20 Sep. 2022 - Deep Learning Approach for classifying Bacteria Types Using morphology of Bacterial Colony
Oral presentation, English, EMBC2022, EMBC2022, イギリス グラスゴー
13 Jul. 2022 - HNSignal Processing of I and Q Output From Doppler Radar to Acquire Vital Signs
Prof. Koichiro Ishibashi
Invited oral presentation, English, Keynote Speech Workshop on Intelligent Signal Processing for Communications, Invited
16 Jun. 2022 - 低電力LoRaモジュールの各低電力モードによる間欠動作の低電力化
吉川祐太; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会総合大会, online
Mar. 2022 - Possibility of Beat Sensors with LoRa Powered by RF Energy Harvesting
Koichiro Ishibashi; Tran Tuan Anh; Shuntaro Saku
Invited oral presentation, English, International Workshop on Convergence Platform for IoT Based Smart Monitoring Systems, Conference room, 9th Floor, S1 building, Le Quy Don Technical University (LQDTU), No. 236 Hoang Quoc Viet Str., Hanoi, Vietnam, online, International conference
23 Dec. 2021 - A Sub uW and 14bit Resolution Temperature Sensor for IoT Using Thermistor-Defined TDC
Hung-NGUYEN; TRONG,Van-TRUNG NGUYEN; Koichiro ISHIBASHI
Oral presentation, English, 電子情報通信学会総合大会通信学会 研究会 デザインガイア2021 -VLSI設計の新しい大地, online
Dec. 2021 - nW級 920 MHz WuRxの研究
柴崎周人
Oral presentation, Japanese, 東京工業大学 MCRG - 電気通信大学 AWCC Open House, online
Nov. 2021 - RFEH電源で動作するsub uW 1chip温度センサRFタグの研究,
大塚健吾
Oral presentation, Japanese, 東京工業大学 MCRG - 電気通信大学 AWCC Open House 2021, online
Nov. 2021 - Bacteria Shape Classification using Small-Scale Depth-wise Separable CNNs
Duc-Tho Mai; Koichiro Ishibashi
Oral presentation, English, 43rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, online, https://embc.embs.org/2021/
01 Nov. 2021 - MCU Process Vital Sign Acquisition using Contactless Doppler Radar
Koichiro Ishibashi
Oral presentation, English, TECHNICAL PROGRAM IN DETAIL Symposium on Computer Science and Engineering, TECHNICAL PROGRAM IN DETAIL Symposium on Computer Science and Engineering, Ho Chi Minh City, Vietnam,
23 Oct. 2021 - Infectious Disease Screening system using Medical Radar and Data Quality Assessment by Efficient Neural Network Hardware
Koki Kumagai; Duc-Tho Mai; Guanghao Sun; Koichiro Ishibashi
Oral presentation, English, TECHNICAL PROGRAM IN DETAIL Symposium on Computer Science and Engineering, Ho Chi Minh City, Vietnam/ Online
23 Oct. 2021 - Infectious Disease Screening system using Medical Radar and Data Quality Assessment by Efficient Neural Network Hardware
Koki Kumagai; Duc-Tho Mai; Koichiro Ishibashi
Oral presentation, English, SCSE 2021, Ho Chi Minh City
22 Oct. 2021 - MCU Process Vital Sign Acquisition using Contactless Doppler Radar
Koichiro Ishibashi; Hideyuki Tsujimoto
Invited oral presentation, English, SCSE 2021, International conference
22 Oct. 2021 - 電波発電のためレクテナとIoT応用技術
石橋孝一郎
Others, Japanese, JST(科学技術推進機構) CRESTブース内, CEATEC 2021 Online, Online
19 Oct. 2021 - A Low‐Power Low‐Area SoC based in RISC‐V Processor for IoT Applications
Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Khai‐Duy Nguyen; Trong‐Thuc Hoang; Koichiro Ishibashi; Cong‐Kha Pham
Oral presentation, English, International SoC Design Conference 2021, Ramada Plaza Jeju Hotel, Jeju, Korea
08 Oct. 2021 - 高精度、長時間動作、長距離通信を実現するBeat Sensor技術
石橋孝一郎
Public discourse, Japanese, JEITA スマートセンシング・デバイス融合技術分科会
11 Sep. 2021 - PV and RF Hybrid Energy Harvesting Power Supply
Shuntaro Saku; Koichiro Ishibashi
Oral presentation, English, NICT ASEAN IVO Workshop, Hanoi(online)
06 Aug. 2021 - T Beat Sensors for monitoring CO2 to detect luck of ventilation in Covid-19 environment
Koichiro Ishibashi
Oral presentation, English, NICT ASEAN IVO Workshop, Invited, Hanoi, Vietnam, online, International conference
06 Aug. 2021 - Bacteria Shape Recognition with the Kotobuki’s model
Duc-Tho Mai; Koichiro Ishibashi
Oral presentation, English, 第60回日本生体医工学会, オンライン開催
17 Jun. 2021 - Transfer Characteristics of CMOS Inverter using "Steep SS PN-Body Tied SOI-FET"
Shota Ishiguro; Jiro Ida; Takayuki Mori; Koichiro Ishibashi
Oral presentation, English, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan
19 Apr. 2021 - Analysis of Drain Current Enhancement in “PN-Body Tied SOI-FET
Hiroki Ito; Jiro Ida; Takayuki Mori; Koichiro Ishibashi
Oral presentation, English, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan
19 Apr. 2021 - Infection Diseases Screening System by Contactless Radar and Machine Learning AI
Koichiro Ishibashi
Oral presentation, English, JST日台研究交流「AIシステム構成に資するナノエレクトロニクス技術」 ワークショップ, Invited, JST日台研究交流「AIシステム構成に資するナノエレクトロニクス技術」 ワークショップ, online, Domestic conference
13 Apr. 2021 - Low-Power and Long-Range Water Level Monitoring Beat Sensor with LoRa modules
Maki Kajiura; Yuta Yoshikawa; Koichiro Ishibashi
Oral presentation, English, Advanced Wireless Communications, Energy Harvesting and IoT Sensors for Smart Monitoring Systems, Hanoi, Vietnam (On line)
27 Mar. 2021 - The Project for Industrialization of RF Energy Harvesting Technology by JST CREST
Koichiro Ishibashi; Jiro Ida; Kenji Itoh; Shigeru Makino; Ryo Ishikawa; Koji Ishibashi
Oral presentation, English, Advanced Wireless Communications, Energy Harvesting and IoT Sensors for Smart Monitoring Systems, Hanoi, Vietnam, (On line)
27 Mar. 2021 - The project for industrialization of RF Energy Harvesting Technology by JST CREST
Koichiro Ishibashi
Invited oral presentation, English, ICT Virtual Organization of ASEAN Institutes and NICT ASEAN IVO, Hanoi, Vietnam, online, International conference
26 Mar. 2021 - Low-Power and Long-Range Water Level Monitoring Beat Sensor with LoRa modules
Maki Kajiura; Koichiro Ishibashi
Oral presentation, English, ICT Virtual Organization of ASEAN Institutes and NICT ASEAN IVO
26 Mar. 2021 - マイコンを用いたドップラーレーダ信号による高精度心拍検出
辻本英之; 石橋孝一郎; 孫光鎬
Oral presentation, Japanese, 2021 年 電子情報通信学会総合大会, on line
12 Mar. 2021 - CRESTにおけるRFエネルギーハーベスティング技術の開発
石橋孝一郎; 井田次郎; 伊東健治; 牧野滋; 石川亮; 石橋功至
Others, Japanese, JEITA IoT向けエネルギーハーベスティングの動向と標準化セミナー
14 Jan. 2021 - Effects of Modulated Waveform on RF Energy Harvesting
Linh Thuy Nguyen; Luong Duy Manh; Koichiro Ishibashi
Oral presentation, English, International Conference on Green and Human Information Technology ICGHIT2021, jeju Island, Korea
13 Jan. 2021 - 非接触医用レーダと品質評価機械学習による高信頼感染症スクリーニング
熊谷洸貴; 石橋孝一郎; 孫 光鎬
Oral presentation, Japanese, 電子情報通信学会、ニューロコンピューティング研究会（NC）
18 Dec. 2020 - Development of Infection Diseases Screening System by Collaboration between Vietnam and Japan
Invited oral presentation, English, Vietnamese Academic Network in Japan (VANJ Conference 2020), Invited, Tokyo Japan. (On line), International conference
28 Nov. 2020 - Non-contact Heartbeat Detection by using CW-Doppler Radar under Respiratory Artifact
Yuki Iwata; Koichiro Ishibashi; Guanghao Sun; Luu Manh Ha; Han Trong Thanh; Nguyen Linh Trung; Do Trong Tuan
Oral presentation, English, The 2nd ASEAN UEC Work Shop on AI and Energy, Bandung, Indonesia (Virtual)
21 Nov. 2020 - nergy harvesting from environment RF for IoT applications
Invited oral presentation, English, International Conference on ICT for Smart Society (ICISS 2021), Bandung, Indonesia (on line), International conference
19 Nov. 2020 - Energy Harvesting from Environment RF for IoT Applications
Invited oral presentation, English, 2020 International Conference on Advanced Technologies for Communications (ATC 2020), Nha Trang, Vietnam, International conference
01 Oct. 2020 - 急峻な SS を持つ“PN-Body Tied SOI-FET”のCMOS インバータ伝達特性
石黒 翔太; 井田 次郎; 森 貴之; 石橋 孝一郎
Oral presentation, Japanese, 一般社団法人 電子情報通信学会 信学技報, THE INSTITUTE OF ELECTRONICS, IEICE Technical Report INFORMATION AND COMMUNICATION ENGINEERS, 2020
Aug. 2020 - CR-SSAによる呼吸及び体動下での非接触な心拍検出
岩田 勇樹; 石橋 孝一郎; 孫 光鎬; ルー マンハ; ハン チョンタイン; グエン リンチュン; ド チョントゥアン
Oral presentation, Japanese, 第59回日本生体医工学会, 岡山大学 （on line）
27 May 2020 - 低電力温度センサーRF TAGの特性
熊谷慎也; 石橋孝一郎
Poster presentation, Japanese, 電子情報通信学会総合大会, 電気情報通信学会, 広島大学
20 Mar. 2020 - Loraを用いたBeat 方式ダストセンサ
吉川祐太; 石橋孝一郎
Poster presentation, Japanese, 2020年電子情報通信学会総合大会, 電子情報通信学会, 広島大学
20 Mar. 2020 - "Super steep SS “PN-Body tied SOI-FET” with 65 nm thin Box FD-SOI"
Keita Daimatsu; Jiro Ida; Takuya Yamada; Takayuki Mori; Koichiro Ishibashi
Oral presentation, English, IEEE ICTA, 2019, Chengdu, China
13 Dec. 2019 - Vital Sign Acquisition Using Doppler Radar under Random Body Movements Rejected by Pca Algorithm
Yuki Iwata; Koichiro Ishibashi; Guaghao Sun
Oral presentation, English, ICBME 2019, The 17th International Conference on Biomedical Engineering, Singapore
10 Dec. 2019 - Vital Sign Acquisition using Doppler Radar under Random Body Movements rejected by PCA Algorithm
Yuki Iwata; Koichiro Ishibashi; Guanghao Sun
Poster presentation, English, ICBME 2019, Singapore, https://icbme.org
09 Dec. 2019 - RFエネルギーハーベスティング向けDCDCコンバータの検討
ムンフツォグ ムンフズル; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会 デザインガイア, 電子情報通信学会, 松山
15 Nov. 2019 - RFエネルギーハーベスティング向け DCDCコンバータの検討
ムンフツォグ; ムンフズル 石橋; 孝
Oral presentation, Japanese, デザインガイア 2019 (IEICE 研究会）, 愛媛 松山, https://www.ieice.org/ken/program/index.php?tgs_regid=e315e43d77dccea547ec3d6d1f427eaaa8b461ec138ab234fbdae60a0be4ff0a&tgid=IEICE-VLD
15 Nov. 2019 - " Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS“PN Body-Tied SOI-FET” and Proposal of CMOS without Vsub Bias "
Wataru Yabuki; Jiro Ida; Takayuki Mori; Koichiro Ishibashi; Yasuo Arai
Oral presentation, English, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S)
14 Oct. 2019 - RF Characteristics of Rectifier Devices for Ambient RF Energy Harvesting
Koichiro Ishibashi; Jiro Ida; Linh-Thuy Nguyen; Ryo Ishikawa; Yasuo Satoh
Invited oral presentation, English, 2019 International Symposium on Electronics and Smart Devices (ISESD), ISESD, インドネシア, International conference
08 Oct. 2019 - RF Characteristics of Rectifier Devices for Ambient RF Energy Harvesting
K. Ishibashi; J. Ida; Linh-Thuy Nguyen; Ryo Ishikawa; Y. Satoh; D. M. Luong
Invited oral presentation, English, IEEE International Symposium on Electronics and Smart Devices, 2019, Bali, Indonesia, International conference
07 Oct. 2019 - Super steep SS “PN-Body tied SOI-FET” with 65 nm thin Box FD-SOI
Keita Daimatsu; Jiro Ida; Takuya Yamada; Takayuki Mori; Koichiro Ishibashi
Oral presentation, English, IEEE ICTA, IEEE, Chengdu, China
Oct. 2019 - Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS“PN Body-Tied SOI-FET” and Proposal of CMOS without Vsub Bias
Wataru Yabuki; Jiro Ida; Takayuki Mori; Koichiro Ishibashi; Yasuo Arai
Oral presentation, English, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S),, IEEE, San Francisco
Oct. 2019 - 急峻なSSを持つ"PN Body-Tied SOI-FET"におけるBOXの中の正電荷と基板バイアスの影響
Public symposium, Japanese
19 Aug. 2019 - 極急峻なSSを持つ"PN-Body Tied SOI-FET"を使った極低電力カレクテナ
Public symposium, Japanese, ICD 集積回路研究会, 北海道 札幌
19 Aug. 2019 - 急峻なSSを持つ“PN Body-Tied SOI-FET”におけるBOX中の固定電荷と基板バイアスの影響
Oral presentation, Japanese, 電子情報通信学会
09 Aug. 2019 - 極急峻SSを持つ"PN-Body Tied SOI-FET"を使った極低電力レクテナ
Oral presentation, Japanese, 電子情報通信学会
09 Aug. 2019 - Beat Sensors for Monitoring Environments IoT Sensors Which Persistently Operate in Environments
Invited oral presentation, English, ECTI-CON, Invited, Pattaya/ Thailand, International conference
19 Jun. 2019 - ドップラーレーダを用いた連続非接触血圧測定
Oral presentation, Japanese, 日本生体医工学会, 沖縄 那覇
19 Jun. 2019 - First Experimental Confirmation of Transient Effect on Super Steep SS “PN-Body Tied SOI FET” with Pulse Measurements
H. Endo; J. Ida; T. Mori; K. Ishibashi; Y. Arai
Oral presentation, English, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, http://ewh.ieee.org/conf/edtm/2019/
13 Mar. 2019 - Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning
Xiaofeng Yang; Koki Kumugai; Guanghao Sun; Koichiro Ishibashi; Le Thi Hoi; Nguyen Vu Trung; Nguyen Van Kinh
Oral presentation, English, 2019 IEEE Sensors Applications Symposium, France
11 Mar. 2019 - スーパースティープトランジスタ整流器を用いたAMラジオ波からの発電
Poster presentation, Japanese, 国際ナノテクノロジー総合展・技術会議, 東京ビッグサイト
30 Jan. 2019 - スーパースティープトランジスタ整流器を⽤いたAMラジオ波からの発電 JST 戦略的創造研究推進事業「微⼩エネルギーを利⽤した⾰新的な環境発電技術の創出」CREST・さきがけ複合領域
石橋孝一郎; 佐藤康夫; 井田次郎; 伊東健治
Poster presentation, Japanese, 早稲田大学公開シンポジウム
07 Nov. 2018 - SOTBプロセスでDTMOS構造を用いたクロスカップルブリッジ型整流昇圧回路を用いたRFエネルギーハーベスティング" JST 戦略的創造研究推進事業「微⼩エネルギーを利⽤した⾰新的な環境発電技術の創出」CREST・さきがけ複合領域
石橋孝一郎
Poster presentation, Japanese, 早稲田大学公開シンポジウム, 早稲田大学
07 Nov. 2018 - First Experimental Confirmation of Ultralow Voltage Rectification by Super Steep Subthreshold Slope “PN-Body Tied SOI-FET” for High Efficiency RF Energy Harvesting and Ultralow Voltage Sensing Tied SOI-FET for High Efficiency RF Energy Harvesting
S. Momose; J. Ida; T. Yamada; T. Mori; K. Itoh; K. Ishibashi; Y. Arai
Oral presentation, English, IEEE S3S Conference, IEEE, San Francisco, USA, http://s3sconference.org/, International conference
16 Oct. 2018 - Beat sensors for long life IoT applications
Koichiro Ishibashi
Invited oral presentation, English, EuroSciCon Wireless and Printing Technology 2018, Invited, EuroSciCon, Lisbon, International conference
17 Sep. 2018 - Beat Sensors for Long Life IoT Applications
Koichiro Ishibashi; Ryohei Takitoge; Duangchak Manyvone
Invited oral presentation, English, EuroSciCon Conference on 3D Printing and Wireless Technology, Lisbon, International conference
Sep. 2018 - 急峻なSSを持つ"PN-body Tied SOI-FET"を使ったごく低電圧整流実験
百瀬 駿; 井田次郎; 山田拓弥; 森 貴之; 伊東健治; 石橋孝一郎; 新井康夫
Oral presentation, Japanese, 集積回路研究会(ICD), 北海道大学, Domestic conference
07 Aug. 2018 - A 65nm SOTB Based-On Code-Modulated Synchronized-OOK Transmitter for Normally-OFF Wireless Sensor Networks
Van-Trung Nguyen; Ryo Ishikawa; koichiro Ishibashi
Oral presentation, English, 集積回路研究会(ICD), 北海道大学, Domestic conference
07 Aug. 2018 - エネルギーハーべスティングBestSensorと応用の可能性～低電力、低コスト、高精度IoTセンサの提案
石橋孝一郎
Invited oral presentation, Japanese, 集積回路研究会(ICD), Invited, 北海道大学, Domestic conference
07 Aug. 2018 - エネルギーハーベスティングBeat Sensorと応用の可能性 ～ 低電力、低コスト、高精度IoTセンサの提案 ～
Invited oral presentation, Japanese, 信学技報, vol. 118, no. 291, SDM2018-76, pp. 59-64, 電子情報通信学会 集積回路研究会, 札幌, Domestic conference
07 Aug. 2018 - "Wireless and Low-Power Water Quality Monitoring Beat Sensors For Agri and Acqua-Culture IoT Applications"
Duangchak Manyvone; Ryohei Takitoge; Koichiro Ishibashi
Oral presentation, English, ECTI-COM2018, Chiang Rai, Thailand, International conference
18 Jul. 2018 - Continuous Cuffless Systolic Blood Pressure Monitoring Scheme Using PPG Sensor and Doppler Radar
Ohata,Tomoyuki; Ishibashi Koichiro; Sun Guanghao
Oral presentation, English, EMBC'2018, Honolulu、Hi,USA, International conference
17 Jul. 2018 - Dengue Fever Detecting System Using Peak-Detection of Data from Contactless Doppler Radar
Yang XiaoFeng; Ishibashi, Koichiro; Sun, Guanghao
Oral presentation, English, EMBC'2018, Honolulu, HI, USA, International conference
17 Jul. 2018 - "Cross-couple DTMOS Rectifier with Floating sub-circuit using 65nm SOTB CMOS technology for uW RF Energy Harvesting"
Shiho TAKAHASHI; Thuy-Linh NGUYEN; Yasuo SATO; Koichiro ISHIBASHI
Oral presentation, English, TJMW2018, Bangkok、Thailand, International conference
27 Jun. 2018 - Rectification of Small Voltage Signal by Super Steep Subthreshold Slope "PN-Body Tied SOI FET" for RF Energy Harvesting
Takuya Yamada; Jiro Ida; Takayuki Mori; ShunMomose; Yasunori Tsuchiya; Kenji Itoh; KoichiroIshibashi
Oral presentation, English, TJMW2018, Bangkok, Thailand, International conference
27 Jun. 2018 - PPG とドップラーレーダを用いた収縮期血圧のカフレス連続測定
大畠 知之; 石橋 孝一郎; 孫 光鎬
Oral presentation, Japanese, 57回生体医工学会, 札幌, Domestic conference
19 Jun. 2018 - Characteristics of 65nm SOTB technology and Low power LSI design using the SOTB technology
Koichiro Ishibashi
Invited oral presentation, English, Wrok Shop on Low-power IC design techniques and applications（FIRST 2018）, Invited, Hanoi Vietnam, International conference
15 Mar. 2018 - RF energy harvesting project using Super Steep Transistor on SOI process
Koichiro Ishibashi
Invited oral presentation, English, Wrok Shop on Low-power IC design techniques and applications（FIRST 2018）, Invited, Hanoi Vietnam, International conference
15 Mar. 2018 - IoT Sensors for Monitoring Water and Applications in Vietnam
Koichiro Ishibashi
Invited oral presentation, English, VACI2018, Invited, International conference
04 Mar. 2018 - "エネルギーハーベ スティングBeat Sensorとその特性 ～ 低コスト・小型・高精度IoTセンサの実現 ～"
石橋孝一郎; 瀧峠 良平
Oral presentation, Japanese, 電子情報通信学会 ＡＳＭ研究会, Domestic conference
30 Jan. 2018 - "エネルギーハーベスティングセンサネットワーク向け ナノワット級外温度センサ回路"
新居 慎也; 石橋 孝一郎
Oral presentation, Japanese, 電子情報通信学会 ＡＳＭ研究会, Domestic conference
30 Jan. 2018 - Short Time and Contact-Less Virus Infection Screening System with Discriminate Function Using Doppler Radar
Xiaofeng Yang; Koichiro Ishibashi; Toshiaki Negishi; Tetsuo Kirimoto; Guanghao Sun
Oral presentation, English, BIC-TA 2017, Harbin, China, International conference
01 Dec. 2017 - IoT SENSOR TECHNOLOGIES TO ADDRESS ISSUES OF ASEAN REGION
Koichiro Ishibashi
Keynote oral presentation, English, RCCIE2017, Invited, Faculty of Computer Science and Engineering Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam, http://www.cse.hcmut.edu.vn/fdse2017/#!/welcome, International conference
29 Nov. 2017 - LOW-POWER ENHANCED TEMPERATURE BEAT SENSOR WITH LONGER COMMUNICATION DISTANCE BY DATA-RECOVERY ALGORITHM
Ryohei Takitoge; Masataka Kishi; Koichiro Ishibashi
Oral presentation, English, IEEE Sensors2017, Glasgow,Scotland,UK, International conference
29 Oct. 2017 - A 0.148nJ/conversion 65nm SOTB Temperature Sensor LSI Using ThermistorDefined Current Source
Shinya. Nii; Koichiro. Ishibashi
Oral presentation, English, IEEE S3S CONFERENCE, IEEE, San Francisco, USA, http://s3sconference.org/, International conference
16 Oct. 2017 - Gate Controlled Diode Characteristics of Super Steep Subthreshold Slope PNBody Tied SOI-FET for High Efficiency RF Energy Harvesting
S. Momose; J. Ida; T. Mori; T. Yoshida; J. Iwata; T. Horii; T. Furuta; K. Itoh; K.Ishibashi; Y. Arai
Oral presentation, English, IEEE S3S Conference, IEEE, San Francisco, USA, http://s3sconference.org/, International conference
16 Oct. 2017 - Beat Sensors IoT Technology Suitable for Energy Saving
Koichiro Ishibashi; Ryohei Takitoge; Shohei Ishigaki
Invited oral presentation, English, ICDV2017, Invited, IEEE SSCS Vietnam Chapter,VNU University of Engineering and Technology,REV,IEICE Vietnam Section, Hanoi, Vietnam, http://icdv.uet.vnu.edu.vn/home, International conference
05 Oct. 2017 - DC Current Beat: Wireless and Non-invasive DC Current Sensing Scheme
K. Ishibashi; M. Serizawa; R. Takitoge; S. Ishigaki, T; Ishige
Oral presentation, English, Eurosensors 2017, PARIS FRANCE, http://www.eurosensors2017.eu/, This paper presents a wireless and Non-invasive DC Current (DCC) sensing scheme as
an IoT sensors. A RF module transmits only ID codes to a receiver, and the ID transmissions are
called as “DCC Beat”. The interval time of DCC Beats depend on the inductance of ferrite clamp
which is non-invasively installed at the wire of the DC current to be measured, so that the interval
time corresponds to DC Current. The ID data transmission range reaches up to 50 m with 1.2 mW
operating power using a 2.4 GHz RF module. DC current from 0.2 to 4 A can be measured within
error of 5.7%., International conference
03 Sep. 2017 - 急峻なSSを持つPN-Body Tied SOI FETを用いた高効率RFエネルギーハーベスティング用Gate Controlled Diodeの特性
百瀬 駿; 井田次郎; 森 貴之; 吉田貴大; 岩田潤平; 堀井隆史; 古田貴大; 山田拓弥; 高松大地; 伊東健治; 石橋孝一郎; 新井康夫
Oral presentation, Japanese, 電子情報通信学会、集積回路研究会, 電子情報通信研究学会, 北海道札幌市, http://www.ieice.org/ken/program/index.php?tgs_regid=c8b3a2edce754bf9928e98f4476aad18ebe0070a7aff991734f26cc2d02e8692&tgid=IEICE-ICD&lang=, The gate controlled diode characteristics with our newly super steep subthreshold slope (SS) “PN-Bode Tied SOI FET” was shown for the first time. It shows the low leakage current. We found that the Excellent On-characteristics with an input voltage sufficiently lower than conventional diode. We showed that it is possible to optimize GCD by reviewing gate length and gate width of PN-Body Tied SOI FET`s whose threshold is controlled to around 0V. A rectenna by using high impedance antenna, the possibility of shown input power of micro watt below could be rectified., Domestic conference
31 Jul. 2017 - Non-contact Acquisition of Respiration and Heart Rates Using Doppler Radar with Time Domain Peak-detection Algorithm
Xiaofeng Yang; Guanghao Sun; Koichiro Ishibashi
Oral presentation, English, EMBC ’17, IEEE, Jeju Island, Korea, https://embc.embs.org/2017/, The non-contact measurement of the respiration
rate (RR) and heart rate (HR) using a Doppler radar has
attracted more attention in the field of home healthcare
monitoring, due to the extremely low burden on patients,
unconsciousness and unconstraint. Most of the previous studies
have performed the frequency-domain analysis of radar signals
to detect the respiration and heartbeat frequency. However,
these procedures required long period time (approximately 30
s) windows to obtain a high-resolution spectrum. In this study,
we propose a time-domain peak detection algorithm for the fast
acquisition of the RR and HR within a breathing cycle
(approximately 5 s), including inhalation and exhalation. Signal
pre-processing using an analog band-pass filter (BPF) that
extracts respiration and heartbeat signals was performed., International conference
11 Jul. 2017 - Possibility of Super Steep Subthreshold Slope Devices for High Efficiency RF Energy Harvesting of Ultra Low Power Input
Jiro Ida; Kenji Itoh; Koichiro Ishibashi
Invited oral presentation, English, TJMW2017, Invited, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, Bangkok, Thailand, http://www.ieice.org/~mw/TJMW2017/, International conference
14 Jun. 2017 - RF Characteristics of SOTB Devices for GHz Frequency Applications
Nguyen Van Trung; Koichiro Ishibashi
Oral presentation, English, TJMW2017, Invited, IEICE Technical Committee, Bangkok, Thailand, http://www.ieice.org/~mw/TJMW2017/, The paper presents RF characteristics of the 65nm SOTB CMOS devices for 1GHz range. With many superior features such as high transconductance gm, low leakage current, low threshold voltage, high resistivity substrate, small parasitic capacitance and so on, SOTB devices promise as a good candidate for RF applications. The SOTB 65nm NMOS and PMOS was laidout with total channel width WT = 1.2um, channel length L = 0.06um and the structure of patterns are suitable for measurement using 12-pin Cascade Unity probe. The measured results show strong effects of long wire between gate and pad on high-frequency figure of merit of SOTB devices, even at low frequency range of 1GHz . Besides, simulation results expose a hopeful potential of SOTB devices for RF applications, International conference
14 Jun. 2017 - Advantages of Power and Temperature Beat Sensors for IoT Applications
Koichiro ISHIBASHI; Ryohei TAKITOGE; Shohei ISHIGAKI
Invited oral presentation, English, VJMW 2017, Invited, IEICE Technical Committee on Microwaves, Hanoi,Vietnam, http://vjmw2017.hust.edu.vn/, International conference
13 Jun. 2017 - Review of Steep Subthreshold Slope Devices and its possibility for High Efficiency RF Energy Harvesting
Jiro IDA; Kenji ITOH; Koichiro ISHIBASHI
Invited oral presentation, English, VJMW2017, Invited, IEICE Technical Committee on Microwaves, Hanoi,Vietnam, http://vjmw2017.hust.edu.vn/, The research status of steep subthreshold slope (SS) devices for LSI’s on the Ultra low power IoT systems is reviewed, and our
newly proposed super steep SS “PN- Body Tied SOI FET” is introduced. The diode technology for RF energy harvesting is also reviewed
and the possibility of the high efficiency rectification for the ultralow input on the RF energy harvesting are shown with our “PN- Body Tied
SOI FET”., International conference
13 Jun. 2017 - A 910nW Delta Sigma Modulator using 65nm SOTB Technology for Mixed Signal IC of IoT Applications
Koichiro Ishibashi; Junya Kikuchi; Nobuyuki Sugii
Invited oral presentation, English, IEEE International Conferenceon IC Design and Technology (ICICDT 2017), Invited, IEEE, Austin, Texas, USA, http://ewh.ieee.org/conf/icicdt/downloads/2017_ICICDT_conferenceprogram.pdf, Ultra-low-power integrated circuits are key to achieve IoT system which operate with small batteries or even energy harvesting. This paper demonstrates design of low power digital analog circuits using 65nm SOTB (Silicon on Thin Buried oxide) technology, the performance of which is suitable for IoT system. They include 13.4pJ/cycle 0.14uA Sleep Current CPU with 15nA VBB generator, 910nW 46fJ/conv 0.036mm2 Modulator, 1.36uW 315MHz Synchronized-OOK Receiver., International conference
23 May 2017 - ドップラーレーダを用いた時間領域ピーク検出アルゴリズムによる呼吸と心拍の非接触測定
楊 小鳳; 石橋孝一郎
Oral presentation, Japanese, 第56回日本生体医工学会大会, 日本生体医工学会, 宮城県仙台市, http://www2.idac.tohoku.ac.jp/jsmbe56/, Domestic conference
03 May 2017 - IoT Sensor technologies and Applications in ASEAN Region
Koichiro Ishibashi; Tran Ngoc Thinh; Guanghao Sun
Invited oral presentation, English, IUUWS2017, The University of Electro-Communications, Chofu,Tokyo, Japan, http://gakusei.office.uec.ac.jp/iuuws2017/index.html, Trillion sensor universe in which trillions of sensors are distributed to gather the data of the internet is expected in early 2020s[1], thereby addressing various issues such as agriculture, aquaculture, environment, energy, healthcare, and so on. These are many possibilities that these IoT sensor technologies play important roles on addressing various issues on ASEAN region, which economy has been growing rapidly so that various issues have been occurred. This paper introduces technologies to realize IoT sensors, and some application examples using the IoT sensors which could address the issues on those countries., International conference
27 Mar. 2017 - 同期通信MACプロトコルによるセンサノードの低電力化の検討
石垣翔平; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会、スマート無線研究会, 電子情報通信学会、スマート無線研究会, 愛媛県松山市, http://www.ieice.org/ken/program/index.php?tgs_regid=afb0822f7654370769cf62c7ecfa29b0350480ba520c4e852f9dd8ba8bc784ad&tgid=IEICE-SR&lang=
19 Jan. 2017 - Temperature Beat: Persistent and Energy Harvesting Wireless Temperature Sensing Scheme
Ryohei Takitoge; Shohei Ishigaki; Tsuyoshi Ishige; Koichiro Ishibashi
Oral presentation, English, ＩＥＥＥ ＳＥＮＳＯＲＳ ２０１６, International conference
02 Nov. 2016 - Evaluation of Applying Spectrum Spreading to Synchronized-OOK Modulation Scheme
Nguyen Van TRUNG; KOICHIRO Ishibashi
Oral presentation, English, IWMST-2016, NCUT、HEU、KIT、UEC、WUST, 台湾 台北, he paper presents a method that applies Spread-Spectrum (SS) technique to synchronized On-Off-Keying (S-OOK) modulation scheme. Different from conventional Direct-sequence SS (DSSS) modulation scheme in which PN code is multiplied with data bit during whole bit duration, in new scheme data bits are transformed into synchronized-DATA (SDATA) before being multiplied with the PN code for synchronized pulse durations. Therefore, transceiver system will show a good interference immunity and energy efficiency. In this paper, the architecture of transmitter (TX) and waveform operation of this modulation scheme are introduced. These were evaluated by simulating on MATLAB/SIMULINK version 9.0 (R2016a).
Key words Wireless Sensor Network (WSN), Transmitter (TX), Receiver (RX), Synchronized-OOK (S-OOK) modulation, Spread-Spectrum (SS), Direct-Sequence (DS), MATLAB/SIMULINK., International conference
31 Oct. 2016 - Design of -30dBm Sensitivity and Sub 10nW Wake-up Receiver for Wireless Sensor Networks Using Body Boost on 65nm SOTB Technology
Tsuyoshi Ishige; Koichiro Ishibashi
Oral presentation, English, ATC2016, International conference
13 Oct. 2016 - エナジーハーベスティング向けシュミット・トリガ付きLDO回路
高橋史帆; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会 ソサエティ大会
22 Sep. 2016 - ドップラーレーダーとArduinoによるローコスト・小型非接触心拍・呼吸計測システムの開発
楊小鳳; 石橋孝一郎; 孫光鎬
Oral presentation, Japanese, 生体医工学シンポジウム2016
17 Sep. 2016 - 13th APT Telecommunication and ICT Development Forum (ADF-13) by APT
Koichiro Ishibashi
Others, English, 13th APT Telecommunication and ICT Development Forum (ADF-13) by APT
Aug. 2016 - 間欠動作センサネットワークシステムにおける低電力同期通信方式の検討
石垣翔平; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会 総合大会 2016
16 Mar. 2016 - ベトナムエビ養殖場水質モニターから見たIoTの課題と効果
石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会 総合大会 2016
16 Mar. 2016 - 論理回路の極低電力動作を実現する基板バイアス発生回路
小出知明; 石橋孝一郎; 杉井信之
Oral presentation, Japanese, 電子情報通信学会 デザインガイヤ
02 Dec. 2015 - SOTB MOSFETを用いた低電力マイクロコントローラの動的基板バイアス制御機構の実装と予備評価
奥原 颯; 小出知明; Johannes maximilian kuehn; Akram Ben Ahmed; 石橋孝一郎; 天野英晴
Oral presentation, Japanese, 電子情報通信学会 デザインガイヤ
02 Dec. 2015 - センサネットワークによるベトナムえび養殖場水質モニター
石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会 ICD研究会
26 Nov. 2015 - A 400mV 0.59mW Low-power CAM-based Pattern Matching System on 65nm SOTB Process
Duc-Hung Le; Nobuyuki Sugii; Shiro Kamohara; Hong-Thu Nguyen; Koichiro Ishibashi; Cong-Kha Pham
Oral presentation, English, TENCON 2015
01 Nov. 2015 - Designs of Ultra-Low-Power and Ultra-Low-Leakage 65nm-SOTB LSI for IoT Applications
Koichiro Isibashi
Oral presentation, English, IEEE S3S Conference 2015
05 Oct. 2015 - SOTB Technology, which Enables Perpetually Reliable CPU for IoT Applications
K. Ishibashi; N. Sugii; K. Kobayashi; T. Koide; H. Nagatomi; S. Kamohara
Oral presentation, English, Fourth Berkeley Symposium on Energy Efficient Electronic Systems
01 Oct. 2015 - Power Beat: A Low‐cost and Energy Harvesting Wireless Electric Power Sensing Scheme for BEMS
Shohei Ishigaki; Koichiro Ishibashi
Oral presentation, English, ICBEST 2015, シンガポール, International conference
31 Aug. 2015 - Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process
Le, Duc-Hung; Sugii, Nobuyuki; Kamohara, Shiro; Nguyen; Xuan-Thuan; Ishibashi, Koichiro; Pham, Cong-Kha
Oral presentation, English, 2015 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
Jun. 2015 - くし歯型MEMS共振器の共振特性と蓄積エネルギー
永村真也; 石毛剛志; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会2015総合大会
11 Mar. 2015 - ZigBeeを用いたセンサネットワークシステム用エナジーハーベスト電源システムの設計法
綿引 亮; 石橋孝一郎; Hieu V. Bui; Thinh N. Than
Oral presentation, Japanese, 電子情報通信学会2015総合大会
10 Mar. 2015 - ルーターの間欠動作によるセンサネットワークシステムの低電力化
諸橋翔太朗; 石橋孝一郎; 床井義之; 伊良皆千里
Oral presentation, Japanese, 電子情報通信学会2015総合大会
10 Mar. 2015 - Low Power Channel Scanning with Contiki's IPv6 Stack for Wireless Sensor Network
Tran Ngoc Thinh; Tu Nguyen; Bui Van Hiev; Koichiro Ishibashi
Oral presentation, English, ACOMP 2014
20 Nov. 2014 - A 0.75V 0.574mW 2.16GHz - 3.2GHz Differential Multipass Ring Oscillator on 65nm SOTB CMOS Technology
Minh-Thien Hoang; Nobuyuki Sugii; Koichiro Ishibashi
Oral presentation, English, ICDV 2014
14 Nov. 2014 - Perpetuum-Mobile Sensor Network Systems using a CPU on 65nm SOTB CMOS Technology
Koichiro Ishibashi; Cong-Kha Pham; Nobuyuki Sugii
Invited oral presentation, English, ICDV 2014, International conference
14 Nov. 2014 - A CARD SIZE ENERGY HARVESTING ELECTRIC POWER SENSOR FOR IMPLEMENTING EXISTING ELECTRIC APPLIANCES INTO HEMS
Yuki Tsunoda; Chikara Tsuchiya; Yuji Segawa; Hajime Sawaya; Minoru Hasegawa; Koichiro Ishibashi
Oral presentation, English, IEEE SENSORS 2014
02 Nov. 2014 - A 36nA Thermal Run-away Immune VBB Generator Using Dynamic Substrate Controlled Charge Pump for Ultra Low Sleep Current Logic on 65nm
H. Nagatomi; N. Sugii; S. Kamohara; K. Ishibashi
Oral presentation, English, 2014 IEEE S3S Conference
07 Oct. 2014 - A 53μW -82dBm Sensitivity 920MHz OOK Receiver Design Using Bias Switch Technique on 65nm SOTB CMOS Technology
H.M. Thien; N. Sugii; K. Ishibashi
Oral presentation, English, 2014 IEEE S3S Conference
07 Oct. 2014 - Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process
Duc-Hung Le; N. Sugii; S. Kamohara; H. Oda; K. Ishibashi; Cong-Kha Pham
Oral presentation, English, IEEE Region 10 ATC 2014
Oct. 2014 - IoT時代の高効率エレクトロニクスに向けた薄膜BOX-SOI（SOTB)CMOSの超低電圧動作回路およびデバイス技術
蒲原史朗; 杉井信之; 山本芳樹; 槇山秀樹; 山下朋弘; 長谷川拓実; 岡西忍; 柳田博史; 門島勝; 前川径一; 三谷仁; 山縣保司; 尾田秀一; 山口泰男; 石橋孝一郎; 天野英晴; 宇佐美公良; 小林和淑; 水谷朋子; 平本俊郎
Oral presentation, Japanese, 応用物理学会 シリコンテクノロジー分科会
08 Aug. 2014 - A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology
K. Ishibashi; N. Sugii; K. Usami; H. Amano; K. Kobayashi; Cong-Kha Pham; H. Makiyama; Y. Yamamoto; H. Shinohara; T. Iwamatsu; Y. Yamaguchi; H. Oda; T. Hasegawa; S. Okanishi; H. Yanagita
Invited oral presentation, English, 電子情報通信学会 シリコン材料・デバイス研究会
04 Aug. 2014 - A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
S. Kamohara; N. Sugii; K. Ishibashi; K. Usami; H. Amano; K. Kobayashi; Cong-Kha Pham
Poster presentation, English, Hot Chips 2014
Aug. 2014 - Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era
S. Kamohara; N. Sugii; Y. Yamamoto; H. Makiyama; T. Yamashita; T. Hasegawa; S. Okanishi; H. Yanagita; M. Kadoshima; K. Maekawa; H. Mitani; Y. Yamagata; H. Oda; Y. Yamaguchi; K. Ishibashi; H. Amano; K. Usami; K. Kobayashi; T. Mizutani; T. Hiramoto; Low-power Electronics Association; Project
Invited oral presentation, English, 2014 Symposia on VLSI Technology and Circuits, Domestic conference
12 Jun. 2014 - A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology
Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; Takumi Hasegawa; Shinobu Okanishi; Hiroshi Yanagita; Shiro Kamohara; Masaru Kadoshima; Keiichi Maekawa; Tomohiro Yamashita; Duc-Hung Le; Takumu Yomogita; Masaru Kudo; Kuniaki Kitamori; Shuya Kondo; Yuuki Manzawa
Oral presentation, English, Cool Chips XVII, Cool Chips XVII
16 Apr. 2014 - エナジーハーベストセンサネットワーク向け低電力pH測定法
綿引 亮; 石橋孝一郎; Hieu V. Bui
Oral presentation, Japanese, 電子情報通信学会 2014年総合大会, 電子情報通信学会
19 Mar. 2014 - An ultra-low power LNA design using SOTB CMOS devices
Hoang Minh Thien; Koichiro Ishibashi
Oral presentation, English, 2013 Thailand-Japan Micro Wave (TJMW2013)
Dec. 2013 - Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by P/N Control with Back for Ultralow 0 4 Operation
H.Makiyama; Y. Yamamoto; H. Shinohara; T. Iwamatsu; H. Oda; N. Sugii; K. Ishibashi; T. Mizutani; T. Hiramoto; Y. Yamaguchi
Oral presentation, English, 2013 IEDM Technical Program
Dec. 2013 - A 4pA/Gate Sleep Current 65nm SOTB Logic Gates Using On-chip VBB Generator for Energy Harvesting Sensor Network Systems
Hiroki Nagatomi; Le Duc-Hung; Cong-Kha Pham; Nobuyuki Sugii; Shirou Kamohara; Toshiaki; Iwamatsu; Koichiro Ishibashi
Oral presentation, English, The 2013 International Conference on Integrated Circuits, Design, and Verification (ICDV 2013)
Nov. 2013 - Vmin=0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB) — How is the application with "Perpetuum-Mobile" micro-controller with SOTB?
N. Sugii; T. Iwamatsu; Y. Yamamoto; H. Makiyama; H. Shinohara; H. Oda; S. Kamohara; Y. Yamaguchi; K. Ishibashi; T. Mizutani; T. Hiramoto
Invited oral presentation, English, IEEE S3S Conference
Oct. 2013 - A 44NW/10MHz Minimum Power Operation of 50K Logic Gate using 65nm SOTB Devices with Back Gate Control
S. Morohashi; N. Sugii; T. Iwamatsu; S. Kamohara; Y. Kato; C-K. Pham; K. Ishibashi; The University of Electro Communications, Japan; Low-Power Electronics Association; Project; PAGE
Oral presentation, English, 2013 SOI-3DI Subthreshold Microelectronics Technology Unified Conference
Oct. 2013 - Vmin=0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB) — How is the application with "Perpetuum-Mobile" micro-controller with SOTB?
N. Sugii; T. Iwamatsu; Y. Yamamoto; H. Makiyama; H. Shinohara; H. Oda; S. Kamohara; Y. Yamaguchi; K. Ishibashi; T. Mizutani; T. Hiramoto
Invited oral presentation, English, IEEE S3S Conference
Oct. 2013 - A Challenge to Perpetuum Computing using SOTB Technology
Koichiro Ishibashi
Keynote oral presentation, English, ACOMP 2013, ACOMP, Ho Chi Minh City, Vietnam, International conference
Oct. 2013 - Speed Enhancement at Vdd = 0.4 V and Randam τpd Variability Reduction of Silicon on Thin Buried Oxide (SOTB)
H. Makiyama, Y; Yamamoto; H. Shinohara; T. Iwamatsu; H. Oda, N; Sugii; K. Ishibashi and Y; Yamaguchi
Oral presentation, English, International Solid-State Devices and Materials
Sep. 2013 - カンチレバー型MEMS共振器の設計
日下部圭佑; 井上雄策; 長谷川翔一; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会2013年総合大会
21 Mar. 2013 - 既存電気機器電力測定のためのカード型電力センサ
角田祐樹; 堀川哲也; 城野遼太; 綿引 亮; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会2013年総合大会
21 Mar. 2013 - Continuous Challenges for Ultra-Low Power LSI - Technologies, and Their Impact to ITC Societies
Koichiro Ishibashi
Keynote oral presentation, English, IEICE Vietnam Section Lecture Meeting on ICT and Inauguration Ceremony, IEICE Vietnam section, Hanoi, Vietnam, International conference
Mar. 2013 - エレクトロニクス技術による省エネルギー化への貢献
石橋孝一郎
Public symposium, Japanese, 第５回ＴＡＭＡ産学官金サミット, 首都圏産業活性化協会, 電気通信大学
Nov. 2012 - 低電圧・低電力化技術の最新動向
石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会2012年ソサエティ大会
13 Sep. 2012 - 低電圧・低電力技術の最新動向
石橋孝一郎
Others, Japanese, 電子情報通信学会
Sep. 2012 - An On-Chip 250 mA 40 nm CMOS Digital LDO Using Dynamic Sampling Clock Frequency Scaling with Offset-Free TDC-Based Voltage Sensor
Kazuo Otsuga; Masafumi Onouchi; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa
Oral presentation, English, 25th IEEE International System-on-Chip Conference (SOCC2012)
Sep. 2012 - ITの低電力技術の研究動向とLEAPプロジェクトにおける無限動作LSIへの挑戦
石橋孝一郎
Invited oral presentation, Japanese, DAシンポジウム2012 -システムLSI設計技術とDA－, 情報処理学会
Aug. 2012 - 薄膜MOSトランジスタを用いた40nm CMOS高速応答デジタルLDOレギュレータ
小野内雅文; 大津賀一雄; 五十嵐康人; 池谷豊人; 森田貞幸; 石橋孝一郎; 柳沢一正
Oral presentation, Japanese, 電子情報通信学会技術研究報告
Aug. 2012 - Sleep Mode Implementation to ZigBee Router Devices for Wireless Sensor Networks
Ryouta SHIRONO; VU Trong Thien; Kohichiro ISHIBASHI
Oral presentation, English, The 3rd IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012)
Aug. 2012 - Low Power Technologies and Scaling Law Toward Future
Koichiro Ishibashi
Invited oral presentation, Japanese, 電子情報通信学会 集積回路研究会, IEICE-ICD(Integrated Circuits and Devices)
Jan. 2012 - Low Power Technologies and Scaling Law Toward Future
Koichiro Ishibashi
Invited oral presentation, Japanese, 電子情報通信学会 集積回路研究会, IEICE-ICD(Integrated Circuits and Devices)
Jan. 2012 - A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process
Onouchi, M; Otsuga, K; Igarashi, Y; Ikeya, T; Morita, S; Ishibashi, K; Yanagisawa, K
Oral presentation, English, IEEE A-SSCC 2011
Nov. 2011 - On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blockes with trimode power gating structure
K. Jinmyoung; T. Nakura; H. Takata; K. Ishibashi; K. Ikeda; K. Asada
Oral presentation, English, 37th. European Solid-State Circuits Conference
Sep. 2011 - Low Power Technologies and their impact on ITC Societies
Koichiro Ishibashi
Keynote oral presentation, English, The 2011 International Conference on Integrated Circuits and Devices in Vietnam, IEICE, IEEE ICDV 2011, Ha Noi, Vietnam, International conference
Aug. 2011 - Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeday; Kunihiro Asada
Oral presentation, English, 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Apr. 2011 - Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks
J. Kim; T. Nakura; H. Takata; K. Ishibashi; M. Ikeda; K. Asada
Oral presentation, English, VLSI Circuits symposium 2010
2010 - LSI industry requirement to SOI for mobile applications
K. Ishibashi
Oral presentation, English, the 3rd FDSOI Workshop
2010 - A low-power wide-range clock synchronizer with predictive-delay-adjustment scheme for continuous voltage scaling in DVFS control
M. Onouchi; Y. Kanno; M. Saen; S. Komatsu; Y. Yasu; K. Ishibashi
Oral presentation, English, A-SSCC 2009
2009 - Hot-CarrierAC Lifetime Enhancement due to Wire Resistance Effect (WRE) in 45nm CMOS Circuits
N. Mizuguchi; K. Takeuchi; H. Tobe; P. Lee; K. Ishibashi
Oral presentation, English, SSDM 2008
Sep. 2008 - Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs
Y. Kanno; K. Yoshizumi; Y. Yasu; K. Ishibashi; H. Mizuno
Oral presentation, English, VLSI Circuit Symposium
2008 - 厚膜MOS電源スイッチを用いた高速電源遮断技術によるモバイルプロセッサの低電力化
福岡一樹; 小澤治; 森涼; 五十嵐康人; 佐々木敏夫; 倉石孝; 安義彦; 石橋孝一郎
Oral presentation, Japanese, 電子情報通信学会技術研究報告[シリコン材料・デバイス]
23 Aug. 2007 - Adaptive body bias techniques for low power SOC
K. Ishibashi
Invited oral presentation, English, International Solid-State Circuits Conference, IEEE ISSCC 2007 Microprocessor Forum, San Francisco Calfornia, International conference
Feb. 2007 - SOCを低電力化する回路技術とデバイスモデルの課題
石橋孝一郎; 大林茂樹; 永久克己; 谷沢元昭; 塚本康正; 長田健一; 宮崎裕行; 山岡雅直
Invited oral presentation, Japanese, 電子情報通信学会技術研究報告［シリコン材料・デバイス］
26 Jan. 2007 - Adaptive Design of SRAM Memory Cells
K. Ishibashi
Oral presentation, English, " in the special evening session” Chip Breakthroughs and Address Circuit/Device Interactions, IEEE IEDM 2007, Special Evening Session, Washington D.C., USA, International conference
2007 - Adaptive Design of SRAM Memory Cells
K. Ishibashi
Oral presentation, English, " in the special evening session” Chip Breakthroughs and Address Circuit/Device Interactions
2007 - A 65-nm embedded SRAM with Wafer Level Burn-in Mode, Leak-bit Redundancy and E-trim Fuse for Known Good Die
S. Ohbayashi; M. Yabuuchi; Y. Oda; S. Imaoka; K. Usui; T. Yonezu; T. Iwamoto; K. Nii; Y. Tsukamoto; M. Arakawa; T. Uchida; M. Okada; A. Ishii; H. Makino; K. Ishibashi; H. Shinohara
Oral presentation, English, ISSCC 2007
2007 - A 1.92μs-Wake-Up Time Thick-Gate-Oxide Power Switch Technique for Ultra Low-Power Single- Chip Mobile Processors
K. Fukuoka; O. Ozawa; R. Mori; Y. Igarashi; T. Sasaki; T. Kuraishi; Y. Yasu; K. Ishibashi
Oral presentation, English, VLSI Circuit Symposium 2007
2007 - A 1.92μs-Wake-Up Time Thick-Gate-Oxide Power Switch Technique for Ultra Low-Power Single- Chip Mobile Processors
K. Fukuoka; O. Ozawa; R. Mori; Y. Igarashi; T. Sasaki; T. Kuraishi; Y. Yasu; K. Ishibashi
Oral presentation, English, VLSI Circuit Symposium 2007
2007 - Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models
Koichiro Ishibashi; Shigeki Ohbayashi; Katsumi Eikyu; Motoaki Tanizawa; Yasumasa Tsukamoto; Kenichi Osada; Masayuki Miyazaki; Masanao Yamaoka
Oral presentation, English, 2006 International Electron Divices Meeting, IEEE IEDM 2006, San Francisco, Calfornia, International conference
2006 - A 65nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
K. Nii; Y. Masuda; M. Yabuuchi; Y. Tsukamoto; S. Ohbayashi; S. Imaoka; M. Igarashi; K. Tomita; N. Tsuboi; H. Makino; K. Ishibashi; H. Shinohara
Oral presentation, English, VLSI Circuit Symposium 2006
2006 - A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
S. Ohbayashi; M. Yabuuchi; K. Nii; Y. Tsukamoto; S. Imaoka; Y. Oda; M.Igarashi; M. Takeuchi; H. Kawashima; H. Makino; Y. Yamaguchi; K. Tsukamoto; M. Inuishi; H. Makino; K. Ishibashi; H. Shinohara
Oral presentation, English, VLSI Circuit Symposimu 2006
2006 - Low power SOC design using partial-trench-isolation ABC SOI (PTI-ABC SOI) for sub-100-nm LSTP technology
Osamu Ozawa; Kazuki Fukuoka; Yasuto Igarashi; Takashi Kuraishi; Yosihiko Yasu; Yukio Maki; Takashi Ipposhi; Toshihiko Ochiai; Masayoshi Shirahata; Koichiro Ishibashi
Oral presentation, English, Symp. VLSI Circuits 2006
2006 - Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models
Koichiro Ishibashi; Shigeki Ohbayashi; Katsumi Eikyu; Motoaki Tanizawa; Yasumasa Tsukamoto; Kenichi Osada; Masayuki Miyazaki; Masanao Yamaoka
Oral presentation, English, 2006 International Electron Divices Meeting
2006 - Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability
Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara
Oral presentation, English, ICCAD 2005
2005 - オンチップメモリの低電力化と微細化への挑戦
石橋孝一郎
Oral presentation, Japanese, 第９回システムＬＳＩワークショップ, 小倉
2005 - 低消費電力プロセッサ 回路技術とその動向
K. Ishibashi
Oral presentation, Japanese, the Annual Symposium on Advanced Computing Systems and Infrastructures, つくば
2005 - 0.5V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process
Motoi Ichihashi; Haruki Toda; Yasuo Itoh; Koichiro Ishibashi
Oral presentation, English, Symp. VLSI Circuits 2005
2005 - A soft-error hardened latch scheme for SoC in a 90nm technology and beyond
Yoshihide Komatsu; Yukio Arima; Tetsuya Fujimoto; Takahiro Yamashita; Koichiro Ishibashi
Oral presentation, English, 2004 IEEE Custom Integrated Circuits Conference
May 2004 - An on-chip active decoupling circuit to suppress crosstalk in deep sub-micron CMOS mixed-signal SoCs
Toshiro Tsukada; Yasuyuki Hashimoto; Kohji Sakata; Hiroyuki Okada; Koichiro Ishibashi
Oral presentation, English, IEEE International Sold-State Circuits Conference
Feb. 2004 - Cosmic-ray immune latch circuit for 90nm technology and beyond
Yukio Arima; Takahiro Yamashita; Yoshihide Komatsu; Tetsuya Fujimoto; Koichiro Ishibashi
Oral presentation, English, IEEE International Solid-State Circuits Conference
Feb. 2004 - Low Power Technology Development at STARC
Koichiro Ishibashi
Oral presentation, English, The Second International Workshop on Nanoelectronics for Terra-bit Information Processing
Jan. 2004 - 論理回路の低電力技術とボディーゲーティング法の提案
石橋孝一郎
Oral presentation, Japanese, SEMI FORUM JAPAN 2004, プロセスデバイス技術セミナー, 大阪
2004 - Low power SoC project at STARC: low voltage and high speed digital and analog circuits
K. Ishibashi
Oral presentation, English, Seminar @IMEC, Leuven, Belgium
07 Nov. 2003 - Low Power SoC Project in STARC
K. Ishibashi; T. Yamashita
Oral presentation, English, 2003 International Symp. on VLSI technology, Systems and Applications
Oct. 2003 - Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um generic CMOS technology
Hiroyuki Okada; Yasuyuki Hashimoto; Kohji Sakata; Toshiro Tsukada; Koichiro Ishibashi
Oral presentation, English, Proceedings of the 29th European Solid-State Circuits Conference
Sep. 2003 - デバイス・回路技術者協議：ゲートリーク問題は誰が解くか？
石橋孝一郎; 野瀬浩一; 若林整; 小林胤雄; 杉井寿博; 黒田忠広; 高柳万里子
Oral presentation, Japanese, 電子情報通信学会技術研究報告［シリコン材料・デバイス］
22 Aug. 2003 - 低電力SoCを目指すSTARCの低電力技術開発
石橋孝一郎; 藤本徹哉; 岡田博之; 山下高廣
Invited oral presentation, Japanese, 電子情報通信学会技術研究報告［シリコン材料・デバイス］
21 Aug. 2003 - A9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs
石橋孝一郎; 山下高廣; 有馬幸生; 峯松勲; 藤本徹哉
Oral presentation, English, 電子情報通信学会技術研究報告［集積回路］
29 May 2003 - 16.7A/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors
長田健一; 斉藤良和; 石橋孝一郎
Oral presentation, English, 電子情報通信学会技術研究報告［集積回路］
28 May 2003 - 16.7fA/Cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors
Kenichi Osada; Yoshikazu Saitoh; Eishi Ibe; Koichiro Ishibashi
Oral presentation, English, IEEE International Sold-State Circits Conference
Feb. 2003 - A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs
Koichiro Ishibashi; Takahiro Yamashita; Yukio Arima; Isao Minematsu; Tetsuya Fujimoto
Oral presentation, English, IEEE International Solid-State Circuits Conference
Feb. 2003 - 論理回路のソフトエラー：低電力ＬＳＩの新しい課題
石橋孝一郎
Invited oral presentation, Japanese, ＳＴＲＪ２００３年度ワークショップ
2003 - 90-65nmテクノロジーに対応できるオンチップメモリは？
石橋孝一郎; 川嶋将一郎; 平木充; 中瀬泰伸; 石井智之; 杉林直彦; 宮野信治
Oral presentation, Japanese, 電子情報通信学会技術研究報告［集積回路］
12 Apr. 2002 - ＳＴＡＲＣにおける低電力技術開発
石橋孝一郎
Oral presentation, Japanese, 第６回システムＬＳＩワークショップ
2002 - A V-driver circuit for lowering power of sub-0.1/spl mu/m bus
Y. Arima; K. Ishibashi; T. Yamashita
Oral presentation, English, 2002 Asia-Pacific ASIC
2002 - 0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme
M. Yamaoka; K. Osada; K. Ishibashi
Oral presentation, English, 2002 Symposium on VLSI Circuits
2002 - Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder
K. Aisaka; T. Aritsuka; K. Ishibashi; H. Kawaguchi; S. Misaka; T. Sakurai; K. Toyama; K. Uchiyama
Oral presentation, English, 2002 Symposium on VLSI Circuits
2002 - CMOS process compatible ie-flash(inverse gate electrode flash) technology for system-on-a chip
Shoji Shukuri; Kazumasa Yanagisawa; Koichiro Ishibashi
Oral presentation, English, 2001 IEEE Custom Integrated Circuits Conference
May 2001 - Substrate-Bias Techniques for SH4（未刊行論文）
K. Ishibashi
Oral presentation, English, in the short course, 2001 VLSI Circuit Symposium, Kyoto
2001 - Low Power Memory
K. Ishibashi
Oral presentation, English, in the short course, 2001 SSDM(International Symposium on Solid-State Devices and Materials), Tokyo
2001 - A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit
M. Yamaoka; K. Yanagiwawa; S. Shukuri; K. Norisue; K. Ishibashi
Oral presentation, English, 2001 Symposium on VLSI Circuits
2001 - CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip
K. Ishibashi; S. Shukuri; K. Tanagisawa
Oral presentation, English, 2001 CICC
2001 - Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell
K. Osada; J. Shin; M. Khan; Y. Liou; K. Wang; K. Shoji; K. Kuroda; S. Ikeda; K. Ishibashi
Oral presentation, English, 2001 IEEE International Solid-state Circuits Conference
2001 - Quantitative Study of SA-Vt CMOS Scheme Based on the Evaluation of Device Fluctuation
G. Ono; M. Miyazaki; K. Ishibashi
Oral presentation, English, 2000 International Conference on Solid State Devices and Materials
2000 - A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias
M. Miyazaki; G. Ono; T. Hattori; K. Shiozawa; K. Uchiyama; K. Ishibashi
Oral presentation, English, 2000 IEEE International Solid-State Circuits Conference
2000 - A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode.
H. Mizuno; K. Ishibashi; T. Shimura; T. Hattori; S. Narita; K. Shiozawa; S . Ikeda; K.Uchiyama
Oral presentation, English, 1999 IEEE International Solid-state Circuits Conference
1999 - A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems
M. Miyazaki; K. Ishibashi
Oral presentation, English, AP-ASIC '99. The First IEEE Asia Pacific Conference
1999 - A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
H. Mizuno; K. Ishibashi
Oral presentation, English, 1998 IEEE International Solid-state Circuits Conference
1998 - A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSls
M. Miyazaki; H. Mizuno; K. Ishibashi
Oral presentation, English, 1998 International Symposium on Low Power Electronics and Design
1998 - A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit
O. Nishii; F. Arakawa; K. Ishibashi; S. Nakano; T. Shimura; K. Suzuki; M. Tachibana; Totsuka; T. Tsunoda; K. Uchiyama; T. Yamada; T. Hattori; H. Maejima; N. Nakagawa; S. Narita; M. Seki; Y. Shimazaki; R. Satomura; T. Takasuga; A. Hasegawa
Oral presentation, English, 1998 IEEE International Solid-state Circuits Conference
1998 - A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS
H. Mizuno; M. Miyazaki; K. Ishibashi; Y. Nakagome; T. Nagano
Oral presentation, English, 1997 Symposium on VLSI Circuits
1997 - The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS
K. Ishibashi; H. Higuchi; Y. Shimbo; F. Arakawa; O. Nishii; N. Nakagawa; H. Maejima; K. Osada; K. Norisue; R. Satomura; H. Aoki; Y. Shimazaki; K. Tanaka; T. Hattori; K. Shiozawa; K. Kudo; K. Uchiyama; S. Narita; J. Nishimoto; T. Nagano; S. Ikeda; K. Kuroda; T. Takeda; N. Hashimoto
Oral presentation, English, 1997 Symposium on VLSI Circuits
1997 - A Lean-power Gigascale LSI Using Hierarchical Vbb Routing Scheme With Frequency Adaptive Vt CMOS
K. Osada; H. Higuchi; K. Ishibashi; N. Hashimoto; K. Shiozawa
Oral presentation, English, 1997 IEEE International Solid-state Circuits Conference
1997 - A cost-oriented two-port unified cache for low-power RISC microprocessors
H. Mizuno; K. Ishibashi
Oral presentation, English, 1996 Symposium on VLSI CIrcuits
1996 - A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators
H. Mizuno; N. Matsuzaki; K. Osada
Oral presentation, English, 1996 IEEE International Solid-state Circuits Conference
1996 - A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL
K. Ishibashi; K. Komiyaji; H. Toyoshima; R. Minami; N. Ohki; H. Ishida; T. Yamanaka; T .Nagano; T. Nishida
Oral presentation, English, 1995 IEEE International Solid-state Circuits Conference
1995 - A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
S. Narita; K. Ishibashi; S. Tachibana; K. Norisue; Y. Shimazaki; J. Nishimoto; K. Uchiyama; T. Nakazawa; K. Hirose; I. Kudoh; R. Izawa; S. Matsui; S. Yoshioka; M. Yamamoto; I. Kawasaki
Oral presentation, English, 1995 Symposium on VLSI Circuits
1995 - An automatic-power-save cache memory for low-power RISC processors
Y. Shimazaki; K. Ishibashi; K. Norisue; S. Narita; K. Uchiyama; T. Nakazawa; I. Kudoh; R. Izawa; S. Yoshioka; S. Tamaki; S. Nagata; I. Kawasaki; K. Kuroda
Oral presentation, English, IEEE Symposium on Low Power Elevtronics and design 1995
1995 - A 6.93-μm2 n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
M. Minami; N. OhkiH. Ishida; T. Yamanaka; A. Shimizu; K. Ishibashi; A. Satoh; T. Kure; T. Nishida; T. Nagano
Oral presentation, English, 1995 Symposium on VLSI Technology
1995 - A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers
K. Ishibashi; K. Takasugi; K. Komiyaji; H. Toyoshima; T. Yamanaka; A . Fuk ami; N.Hashimoto; N. Ohki; A. Shimizu; T. Hashimoto; T. Nagano; T. Nishida
Oral presentation, English, 1994 Symposium on VLSI Circuits
1994 - A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs
Shuji Ikeda; Kyoichiro Asayama; Naotaka Hashimoto; Eri Fujita; Yasuko Yoshida; Atsuyosi Koike; Toshiaki Yamanaka; Koichiro Ishibashi; Satoshi Meguro
Oral presentation, English, IEDM Tech. Dig.
Dec. 1993 - A 12.5ns 16Mb CMOS SRAM
K. Ishibashi; K. Takasugi; T. Hashimoto; K. Sasaki
Oral presentation, English, 1993 Symposium on VLSI Circuits
1993 - A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier
K. Sasaki; K. Ishibashi; K. Ueda; K. Komiyaji; T. Yamanaka; N.Hashimoto; H.T oyos him a; F .Kojima; A. Shimizu
Oral presentation, English, 1992 IEEE International Solid-state Circuits Conference
1992 - A 1 V TFT-load SRAM using a two-step word-voltage method
K. Ishibashi; K. Takasugi; T. Hashimoto; K. Sasaki
Oral presentation, English, 1992 IEEE International Solid-state Circuits Conference
1992 - Low power, low voltage memories for portable electronics
O. Minato; K. Ishibashi
Oral presentation, English, 1991 International Symposium on Technology, Systems, and Applications
1991 - A 1.7V Adjustable I/O Interface for Low Voltage Fast SRAMs
K. Ishibashi; K. Sasaki; T. Yamanaka; H. Toyoshima; F. Kojima
Oral presentation, English, 1991 Symposium on VLSI Circuits
1991 - ポリPMOS負荷型メモリセルのソフトエラー耐性向上手法
植田清治; 佐々木勝朗; 石橋孝一郎; 山中俊明; 日立製作所中央研究所
Oral presentation, Japanese, 1991年電子情報通信学会秋季大会
1991 - A 5.9 μm2 super low power SRAM cell using a new phase-shift lithography
T. Yamanaka; N. Hasegawa; T. Tanaka; K. Ishibashi; T. Hashimoto; A. Shimizu; N. Hashimoto; K. Sasaki; T. Nishida; E. Takeda
Oral presentation, English, 1990 International Electron Devices Meeting
1990 - A 23 ns 4 Mb CMOS SRAM with 0.5 μA standby current
K. Sasaki; K. Ishibashi; T. Yamanaka; K. Shimohigashi; N. Moriwaki; S. Honjo; S. Ikeda; A Koike; S, Meguro; O. Minato
Oral presentation, English, 1990 IEEE International Solid-state Circuits Conference
1990 - An alpha-immune, 2V supply voltage SRAM using polysilicon PMOS load cell
K. Ishibashi; T. Yamanaka; K. Shimohigashi
Oral presentation, English, 1989 Symposium on VLSI Circuits
1989 - A 9 ns 1 Mb CMOS SRAM
K. Sasaki; S. Hanamura; K. Ishibashi; T. Yamanaka; N. Hashimoto; T. Nishida; K. Shimohigashi; S. Honjo
Oral presentation, English, 1989 IEEE International Solid-state Circuits Conference
1989 - A 25 μm2, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity
T. Yamanaka; T. Hashimoto; N. Hashimoto; T. Nishida; A. Shimuzu; K. Ishibashi; Y. Sakai; K. Shimohigashi; E. Takeda
Oral presentation, English, 1988 Electron Devices Meeting, Technical Digest, International
1988 - A 42ns 1Mb CMOS SRAM
O. Minato; T. Sasaki; S. Honjo; K. Ishibashi; Y. Sasaki; N. Moriwaki; K. Nishimura; Y. Sakai; S. Meguro; M. Tsunematsu; T. Masuhara
Oral presentation, English, 1987 IEEE International Solid-state Circuits Conference
1987 - シリサイドドレイン技術のSRAMへの応用
石橋孝一郎; 湊修; 増原利明; 日立製作所中央研究所
Oral presentation, Japanese, 電子情報通信学会創立70周年記念総合全国大会
1987 - Formation of SPE-CoSi2 Submicron Line by Lift Off Using Selective Reaction
K. Ishibashi; S. Furukawa
Oral presentation, English, 1984 International Conference on Solid-state Devices and Materials
1984 - Si permeable base transistor by metal/semiconductor hetero-epitaxy
K. Ishibashi; S. Furukawa
Oral presentation, English, 1984 International Electron Devices Meeting
1984 - Study on Formation of Solid-Phase-Epitaxial CoSi2 Films and Patterning Effects
K. Ishibashi; H. Ishiwara; S. Furukawa
Oral presentation, English, 1983 International Conference on Solid-state Devices and Materials
1983
Courses
- Innovative Comprehensive Communications Design 1
The University of Electro-Communications - イノベイティブ総合コミュニケーションデザイン1
電気通信大学 - 電子回路学(III類）
The University of Electro-Communications - 電子回路学(III類）
電気通信大学 - International Communication for Science and Technology
The University of Electro-Communications - 国際科学技術コミュニケーション論
電気通信大学 - Information and Communications Technologies for SDGs
The University of Electro-Communications - SDGsを支える情報通信論
電気通信大学 - Electronics Circuit K katei
The University of Electro-Communications - 電子回路学 K課程
電気通信大学 - Special Lecture on Integrated Circuit Design
The University of Electro-Communications - Electronics Circuit
The University of Electro-Communications - Low Power LSI Circuit Design
Danang University, University of Science and Technlogy - Low Power LSI Circuit Design
Danang University, University of Science and Technlogy - Low Power LSI Circuit Design
Ho Chi Minh City University of Science - Low Power LSI Circuit Design
Ho Chi Minh City University of Science - Low Power LSI Circuit Design
Ho Chi Minh City University of Science - 電子回路学 （III類）
The University of Electro-Communications - 電子回路学 （III類）
電気通信大学 - Electronics Circuits
The University of Electro-Communications - 電子回路学 （K課程）
電気通信大学 - Integrated Circuit Design Advanced Course
The University of Electro-Communications - 集積回路設計特論
電気通信大学 - 集積回路特論
The University of Electro-Communications - 集積回路特論
電気通信大学 - 基礎電子回路
The University of Electro-Communications - 基礎電子回路
電気通信大学 - 先進理工学基礎
The University of Electro-Communications - 先進理工学基礎
電気通信大学 - 電子回路学
The University of Electro-Communications - 基礎電気電子回路II
The University of Electro-Communications - 基礎電子工学
The University of Electro-Communications - VLSI Low Power Circuit Design
The University of Electro-Communications - 電子回路学
The University of Electro-Communications - 電子回路学
電気通信大学 - 基礎電気電子回路II
The University of Electro-Communications - 基礎電気電子回路II
電気通信大学 - VLSI Low Power Circuit Design
The University of Electro-Communications - VLSI Low Power Circuit Design
電気通信大学 - 基礎電子工学
The University of Electro-Communications - 基礎電子工学
電気通信大学
Affiliated academic society
Research Themes
- マルチ生体センサの機能的な融合による新型感染症検疫システムの実用化に関する研究
Guanghao Sun
01 Apr. 2019 - 31 Mar. 2021 - Scavenging nW RF energy using Super Steep Transistor and Meta-Material Antenna
JST CREST
01 Oct. 2016 - 31 Mar. 2020 - エネルギーハーベスト電源とこれを活用した低電力データセントリックセンサネットワークシステムの研究
STARC
01 Apr. 2015 - 31 Mar. 2018 - Heterogeneous Wireless Sensor Network Monitoring Water Condition for Strengthening Aquaculture Industry in Vietnam
Asia Pacific Telecommunity (APT)
01 Feb. 2015 - 31 Dec. 2015 - Low Power Wireless Water quality Monitoring System
01 Apr. 2013 - 31 Mar. 2015 - エネルギーハーベスト電源とこれを活用した低電力データセントリックセンサネットワークシステムの研究
半導体理工学研究センター
31 Mar. 2015
Industrial Property Rights
- 無線センサ装置及び無線センサシステム
Patent right, 特願2016-198879, Date applied: 07 Oct. 2016 - 無線電力測定装置
Patent right, 石橋孝一郎, KI201401, Date applied: 14 Jan. 2014 - Low Power Processor
Patent right, 特願2007-101243,P2007-101243, Date applied: 09 Apr. 2007, 特開2007-259463,P2007-259463A, Date announced: 04 Oct. 2007, 特許4521619,P4521619, Date issued: 11 Aug. 2010