Manufacturing technology (mechanical, electrical/electronic, chemical engineering), Electronic devices and equipment

Manufacturing technology (mechanical, electrical/electronic, chemical engineering), Electric/electronic material engineering

2003 - 2012
Yokohama National University

Hole-tunneling Si0.82Ge0.18/Si triple-barrier resonant tunneling diodes with high peak current of 297 kA/cm2 fabricated by sputter epitaxy
Yoshiyuki Suda; Nobumitsu Hirose; Takahiro Tsukamoto; Minoru Wakiya; Ayaka Shinkawa; Akifumi Kasamatsu; Toshiaki Matsui
Applied Physics Letters, 124, 093502-1-093502-6, Feb. 2024, Peer-reviwed
Scientific journal, English

Sn distribution in Ge/GeSn heterostructures formed by sputter epitaxy method
Takahiro Tsukamoto; Kento Ikeno; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, Journal of Crystal Growth, 604, 127045/1-127045/5, 18 Dec. 2022, Peer-reviwed
Scientific journal, English

Increasing the critical thickness of SiGe layers on Si substrates using sputter epitaxy method
Takahiro Tsukamoto; Yosuke Aoyagi; Shouta Nozaki; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, Journal of Crystal Growth, 600, 126900/1-126900/4, 29 Sep. 2022, Peer-reviwed
Scientific journal, English

Direct Growth of Patterned Ge on Insulators Using Graphene
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, J. Phys. Chem. C, 125, 14117-14121, 18 Jun. 2021, Peer-reviwed
Scientific journal, English

Evaluation of crystallinity of lattice-matched Ge/GeSiSn heterostructure by Raman spectroscopy
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, Thin Solid Films, 31, 138646-138646, 31 May 2021, Peer-reviwed
Scientific journal, English

Simple annealing process for producing unique one-dimensional fullerene crystal named fullerene finned-micropillar
T. Onishi; T. Tsukamoto; T. Oya
Corresponding, Scientific Reports, 10, 19270, 06 Nov. 2020, Peer-reviwed
Scientific journal, English

Hole-tunneling Si0.82Ge0.18/Si asymmetric-double-quantum-well resonant tunneling diode with high resonance current and suppressed thermionic emission
Ayaka Shinkawa; Minoru Wakiya; Yuki Maeda; Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Japanese Journal of Applied Physics, IOP PUBLISHING LTD, 59, 8, 080903, 27 Jul. 2020, Peer-reviwed, Hole-tunneling Si0.82Ge0.18/Si asymmetric-double-quantum-well resonant tunneling diodes, designed so that the energy difference between the barrier height of the collector side and the coresonance tunneling energy at the coresonance voltage became larger on the basis of the simulation results of voltage-dependent quantized-level shifts and fabricated with the growth of highly B-doped emitter and collector layers without post-annealing, exhibited a flatter surface and a higher performance with a peak current density of 73 kA cm(-2)and suppressed thermionic emission with a peak-to-valley current ratio of 14.
Scientific journal, English

Increase in Current Density at Metal/GeO2/n-Ge Structure by Using Laminated Electrode
Takahiro Tsukamoto; Shota Kurihara; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, Electronic Materials Letters, 16, 41-46, 19 Nov. 2019, Peer-reviwed
Scientific journal, English

Effects of Low-Temperature GeSn Buffer Layers on Sn Surface Segregation During GeSn Epitaxial Growth
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Toshiaki Matsui; Yoshiyuki Suda
Lead, Electronic Materials Letters, 16, 9-13, 14 Nov. 2019, Peer-reviwed
Scientific journal, English

Crystallinity control of SiC grown on Si by sputtering method
Ryosuke Watanabe; Takahiro Tsukamoto; Koichi Kamisako; Yoshiyuki Suda
JOURNAL OF CRYSTAL GROWTH, ELSEVIER SCIENCE BV, 463, 67-71, Apr. 2017, Peer-reviwed, We investigated a method of controlling the crystallinity of an n-type SiC (n-SiC) layer grown on a p-type 4 degrees-off-axis Si(1 1 1) (p-Si) substrate by our sputtering method for use as SiC/Si devices. An n-SiC layer grown on p-Si at 810 degrees C exhibits columnar 3C-SiC(1 1 1) crystal growth. However, it contains many defects near the n-SiC/p-Si interface. We then propose a method in which a 10-nm-thick nondoped SiC (i-SiC) interlayer is grown at a low temperature of 640 degrees C prior to the growth of the n-SiC layer at 810 degrees C, which results in a decrease in the number of defects at the SiC/p-Si interface and an intensive increase in the crystallinity of the n-SiC, compared with that of n-SiC grown at 810 degrees C without the inter layer, probably via effective interlayer reconstruction and an enhancement in the crystallinity of the i-SiC interlayer itself during the n-SiC growth. Furthermore, the n-SiC/i-SiC-interlayer/p-Si structure was applied as a Si-based solar cell and the energy conversion efficiency of the n-SiC/p-Si solar cell effectively increased with the insertion of the i-SiC interlayer. (C) 2017 Elsevier B.V. All rights reserved.
Scientific journal, English

p-Cu2O/SiOx/n-SiC/n-Si memory diode fabricated with room-temperature-sputtered n-SiC and SiOx
Atsushi Yamashita; Takahiro Tsukamoto; Yoshiyuki Suda
JAPANESE JOURNAL OF APPLIED PHYSICS, IOP PUBLISHING LTD, 55, 12, 124103-1-124103-5, Dec. 2016, Peer-reviwed, We investigated low-temperature fabrication processes for our previously proposed pn memory diode with a p-Cu2O/SiCxOy/n-SiC/n-Si structure having resistive nonvolatile memory and rectifying behaviors suitable for a cross-point memory array with the highest theoretical density. In previous fabrication processes, n-SiC was formed by sputtering at 1113K, and SiCxOy and p-Cu2O were formed by the thermal oxidation of n-SiC and Cu at 1073 and 473 K, respectively. In this study, we propose a pn memory diode with a p-Cu2O/SiOx/n-SiC/n-Si structure, where n-SiC and SiOx layers are deposited by sputtering at room temperature. The proposed processes enable the fabrication of the pn memory diode at temperatures of not more than 473 K, which is used for the formation of p-Cu2O. This memory diode exhibits good nonvolatile memory and rectifying characteristics. These proposed low-temperature fabrication processes are expected to expand the range of fabrication processes applicable to current LSI fabrication processes. (C) 2016 The Japan Society of Applied Physics
Scientific journal, English

Control of surface flatness of Ge layers directly grown on Si (001) substrates by DC sputter epitaxy method
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Takashi Mimura; Toshiaki Matsui; Yoshiyuki Suda
THIN SOLID FILMS, ELSEVIER SCIENCE SA, 592, 34-38, Oct. 2015, Peer-reviwed, The formation of Ge layers on Si (001) substrates with 3.5 Omega cm resistivity by the sputter epitaxy method with DC magnetron sputtering has been investigated. The surface morphology of Ge layers grown on Si substrates depends on the sputtering power and the deposited film thickness of Ge. At the initial stage of film deposition, the higher sputtering power yields smaller and more closely packed Ge islands due probably to an increase in the collision rate of the Ge atoms migrating on the Si substrate, which preserves more compressive strains in the films. With the preserved strains, the surface roughening derived from the strain relaxation is reduced. Furthermore, the surface flatness can be improved with the initially smaller islands and additional deposition; this is probably due to the effect of Ge adatom anchoring at concave areas where many bonding sites are available for stable Ge residence. The root-mean-square surface roughness of a 200-nm-thick Ge layer formed at a sputtering power of 100 W is about 0.23 nm. (C) 2015 Elsevier B.V. All rights reserved.
Scientific journal, English

Low-temperature fabrication technologies of Si solar cell by sputter epitaxy method
Sohei Fujimura; Takahiro Someya; Shuhei Yoshiba; Takahiro Tsukamoto; Koichi Kamisako; Yoshiyuki Suda
JAPANESE JOURNAL OF APPLIED PHYSICS, IOP PUBLISHING LTD, 54, 8, 08KD01-1-08KD01-5, Aug. 2015, Peer-reviwed, We applied an epitaxial n(+)-type Si emitter layer grown on a p-type Si substrate by our environmentally-light-load sputter epitaxy method using RF magnetron sputtering without dopant activation annealing for a Si solar cell. We also applied low-temperature cleaning of the substrate with a hydrogen-fluoride treatment at room temperature prior to the emitter layer growth instead of the conventionally used high-temperature thermal cleaning under vacuum condition. In addition, by our sputter epitaxy method, we determined the optimum temperature for the emitter growth. An emitter layer with good crystallinity is obtained, and the solar cell, formed with an emitter layer grown at the optimum growth temperature of 410 degrees C, exhibits an energy conversion efficiency of 12.3% in 100% aperture ratio equivalent without a texture or an antireflection coat. By the above low-temperature processes, a solar cell can be fabricated with process temperatures below 410 degrees C, which exhibits low temperature processes. (C) 2015 The Japan Society of Applied Physics
Scientific journal, English

Formation of GeSn layers on Si (001) substrates at high growth temperature and high deposition rate by sputter epitaxy method
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Takashi Mimura; Toshiaki Matsui; Yoshiyuki Suda
JOURNAL OF MATERIALS SCIENCE, SPRINGER, 50, 12, 4366-4370, Jun. 2015, Peer-reviwed, GeSn layers are formed on Si substrates by the sputter epitaxy method. Flat GeSn layers with 11.5 % Sn content are obtained. In the X-ray diffraction spectra of the GeSn layers with 11.5 % Sn content grown at 523 K, a sharp Ge (004) peak appears at about 64.5306 degrees and the full width at half maximum is about 0.0984 degrees. However, the surface segregation of Sn is observed in the GeSn layers with 11.5 % Sn content at growth temperatures of 548 K and above in this study, which increases the surface roughness. The crystallinity of the GeSn layers formed on Si substrates strongly depends on the growth temperature, but the primary factor degrading the crystallinity is the large lattice mismatch between Si and GeSn. According to a transmission electron microscope image, some dislocations appear at the interface of the GeSn layer grown at 523 K and Si owing to the large lattice mismatch, but there is no Sn surface segregation and a highly ordered atomic arrangement is observed in the upper region. It is considered that a high deposition rate limits Sn surface segregation and enables the growth of GeSn layers at relatively high temperatures, resulting in improved crystallinity. The band gap of the GeSn layers with 8.4 % Sn content is determined by Fourier transform infrared spectroscopy measurement and is about 0.52 eV, which indicates that band gap narrowing occurs.
Scientific journal, English

Investigation of Sn surface segregation during GeSn epitaxial growth by Auger electron spectroscopy and energy dispersive x-ray spectroscopy
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Takashi Mimura; Toshiaki Matsui; Yoshiyuki Suda
APPLIED PHYSICS LETTERS, AMER INST PHYSICS, 106, 5, 052103-1-052103-4, Feb. 2015, Peer-reviwed, The mechanism of Sn surface segregation during the epitaxial growth of GeSn on Si (001) substrates was investigated by Auger electron spectroscopy and energy dispersive X-ray spectroscopy. Sn surface segregation depends on the growth temperature and Sn content of GeSn layers. During Sn surface segregation, Sn-rich nanoparticles form and move on the surface during the deposition, which results in a rough surface owing to facet formation. The Sn-rich nanoparticles moving on the surface during the deposition absorb Sn from the periphery and yield a lower Sn content, not on the surface but within the layer, because the Sn surface segregation and the GeSn deposition occur simultaneously. Sn surface segregation can occur at a lower temperature during the deposition compared with that during postannealing. This suggests that the Sn surface segregation during the deposition is strongly promoted by the migration of deposited Ge and Sn adatoms on the surface originating from the thermal effect of substrate temperature, which also suggests that limiting the migration of deposited Ge and Sn adatoms can reduce the Sn surface segregation and improve the crystallinity of GeSn layers. (C) 2015 AIP Publishing LLC.
Scientific journal, English

p-Cu2O/SiCxOy/n-SiC/n-Si memory diode having resistive nonvolatile memory and rectifying behaviors
Atsushi Yamashita; Yoshihiko Sato; Takahiro Tsukamoto; Yoshiyuki Suda
APPLIED PHYSICS EXPRESS, IOP PUBLISHING LTD, 7, 7, 074203-1-074203-4, Jul. 2014, Peer-reviwed, We have proposed a pn memory diode having a p-Cu2O/SiCxOy/n-SiC/n-Si diode structure with a SiCxOy layer formed between the pn semiconducting layers. The memory diode shows both resistive-nonvolatile-memory and rectifying behaviors, which are suited for the theoretically densest cross-point memory array. The forward bias current switches between high and low currents corresponding to low- and high-resistance states, respectively. Experimental results suggest that the change in the state is related to the nonexistence or existence of. negative charges generated by electrons trapped in the intermediate SiCxOy oxide layer. This memory also exhibits good endurance characteristics of more than 105 resistance-switching cycles. (C) 2014 The Japan Society of Applied Physics
Scientific journal, English

Planar electron-tunneling Si/Si0.7Ge0.3 triple-barrier resonant tunneling diode formed on undoped strain-relaxed buffer with flat surface
Takafumi Okubo; Takahiro Tsukamoto; Yoshiyuki Suda
APPLIED PHYSICS EXPRESS, IOP PUBLISHING LTD, 7, 3, 034001-1-034001-4, Mar. 2014, Peer-reviwed, We demonstrated a planar electron-tunneling Si/Si0.7Ge0.3 triple-barrier (TB) resonant tunneling diode (RTD) formed via a channel layer on an undoped strain-relaxed quadruple-Si1-xGex-layer (QL) buffer. Compared with a conventional vertical Si/Si0.7Ge0.3 TB RTD formed on a heavily doped QL buffer, the dislocation density is low, the surface is flat, and the resonance current density is much larger. These observations, together with analyses of current voltage (I-V) curve fitting to the physics-based analytical expression, suggest that the enhanced I V characteristics in the planar RTD are related to decreases in the number of crystalline defect states and the structural and potential fluctuations. (C) 2014 The Japan Society of Applied Physics
Scientific journal, English

Effects of DC Sputtering Conditions on Formation of Ge Layers on Si Substrates by Sputter Epitaxy method
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Takashi Mimura; Toshiaki Matsui; Yoshiyuki Suda
2014 7TH INTERNATIONAL SILICON-GERMANIUM TECHNOLOGY AND DEVICE MEETING (ISTDM), IEEE, 97-98, 2014, Peer-reviwed
International conference proceedings, English

Effects of boron dopants of Si (001) substrates on formation of Ge layers by sputter epitaxy method
Takahiro Tsukamoto; Nobumitsu Hirose; Akifumi Kasamatsu; Takashi Mimura; Toshiaki Matsui; Yoshiyuki Suda
Applied Physics Letters, 103, 17, 172103-1-172103-4, 21 Oct. 2013, Peer-reviwed, The formation of Ge layers on boron-doped Si (001) substrates by our sputter epitaxy method has been investigated. The surface morphology of Ge layers grown on Si substrates depends on the substrate resistance, and flat Ge layers are obtained on Si substrates with 0.015 Ω cm resistivity. Highly boron-doped Si substrates cause a transition in the dislocation structure from complex dislocations with 60° dislocation glide planes to 90° pure-edge dislocations, resulting in the formation of flat Ge layers. Furthermore, we have found that the surface morphology of the Ge layers improves with increasing Ge layer thickness. Ge atoms migrating on the deposited Ge layers tend to position themselves at the reactive sites, where the reactivity is related to the number of bonding contacts between the Ge atom and the surface. This modifies the surface morphology, resulting in a flatter surface. Boron dopants together with the sputter epitaxy method effectively suppress the growth of Ge islands and result in the formation of flat Ge layers. © 2013 AIP Publishing LLC.
Scientific journal, English

PN-Diode P-Oxide-Semiconductor/N-SiC/N-Si Resistive Nonvolatile Memory for Cross-Point Memory Array
Yoshihiko Sato; Atsushi Yamashita; Takahiro Tsukamoto; Yoshiyuki Suda
NONVOLATILE MEMORIES 2, ELECTROCHEMICAL SOC INC, 58, 5, 53-57, 2013, Peer-reviwed, We have demonstrated resistive nonvolatile memory devices with the pn-diode structures of p-AgOx/SiOx/n-SiC/n-Si(111) and p-CuOx/SiOx/n-SiC/n-Si(111) which have a good rectifying current-voltage (I-V) characteristic. The forward currents change between high and low, indicating a resistive nonvolatile memory. The I-V and capacitance-voltage (C-V) curve and the structural analyses suggest that existence and nonexistence of trapped electrons in the SiOx layers corresponds to the low and high forward current states, respectively. These memory devices have a well rectifying characteristic feature; they are expected to be suitable to the most theoretically dense cross-point array.
International conference proceedings, English

Layered Structures of Interfacial Water and Their Effects on Raman Spectra in Graphene-on-Sapphire Systems
Hiroki Komurasaki; Takahiro Tsukamoto; Kenji Yamazaki; Toshio Ogino
JOURNAL OF PHYSICAL CHEMISTRY C, AMER CHEMICAL SOC, 116, 18, 10084-10089, May 2012, Peer-reviwed, We investigated the structure of the interfacial water layers between graphene sheets and a sapphire substrate by observing them through graphene sheets at room temperature using atomic force microscopy. When graphene sheets were deposited at low relative humidity, the interfacial water layers appeared as small islands. They grew in layer-by-layer stacking with an increase in the relative humidity. We also investigated effects of the interfacial water layers on Raman spectra from the graphene sheets that cover the water layers. The correlation between G-peak position (intensity) and 2D-peak position (intensity) shows that the interfacial water induces hole-doping in graphene sheets. The doping density increases with increasing the amount of interfacial water. This study shows that the electrical properties of graphene sheets are tunable by controlling the hydrophilicity of substrate surfaces.
Scientific journal, English

Evolution of step morphology on vicinal sapphire (1-102) surfaces accompanied with self-assembly of comb-shaped chemical domains
Hiroki Komurasaki; Toshinari Isono; Takahiro Tsukamoto; Toshio Ogino
APPLIED SURFACE SCIENCE, ELSEVIER SCIENCE BV, 258, 15, 5666-5671, May 2012, Peer-reviwed, Morphology of vicinal sapphire (1 - 102) surfaces was observed in air by atomic force microscopy (AFM) after annealing at temperatures between 1073 K and 1273 K. Surfaces of one type of the samples exhibited high densities of islands and voids with single-atomic height near the step edges at the early stage of annealing, and the crystallographic anisotropy appears as their elongated shapes. During the subsequent annealing, their densities were decreased through the Ostwald ripening process, and finally they were incorporated into the upper and lower terraces. On surfaces of another type of the samples, a combshaped pattern consisting of parallel-striped domains running along the [1 - 10 - 1] direction appeared upon the annealing at 1273 K for 3 h. Difference in hydrophilicity was observed between the striped domains and the other areas using frictional force microscopy, which detects the amount of adsorbed water on the surface through meniscus force. The striped pattern that is one of the features of the surface anisotropy is considered to be formed because the surface energy can be decreased when two striped stress domains are alternately arranged. (C) 2012 Elsevier B.V. All rights reserved.
Scientific journal, English

Effects of Surface Chemistry of Substrates on Raman Spectra in Graphene
Takahiro Tsukamoto; Kenji Yamazaki; Hiroki Komurasaki; Toshio Ogino
JOURNAL OF PHYSICAL CHEMISTRY C, AMER CHEMICAL SOC, 116, 7, 4732-4737, Feb. 2012, Peer-reviwed, We investigated the effects of surface chemistry of substrates on the Raman spectra of graphene flakes that come into contact: with various insulating substrates, such as quartz and sapphire, under ambient conditions at room temperature. The G-peak positions of graphene flakes on such substrates were investigated, and significant blue-shifts of the G-band were observed on a chemically single-phased sapphire (0001) substrate. On a phase-separated sapphire (0001) substrate with Al-terminated (hydrophilic) and O-terminated (hydrophobic) domains, the G-band of graphene flakes was composed of two peaks centered at 1587 cm(-1) (G(1)-peak) and 1593 cm(-1) (G(2)-peak). The G(1)-peak originated from the O-terminated domain and the G2-peak from the Al-terminated one. Since the 2D-peak shifts were small, the Raman shifts in the G-band were attributed to chemical doping from environmental conditions, especially water layers at the graphene/substrate interface that cause hole-doping. The blue-shift in the G-band increased with the increase in the amount of water molecules subject to the surface chemistry of the substrate. Even though Raman spectroscopy is an excellent tool for characterizing the physical properties of graphene, this study indicates that preparation of the substrate surface is important for determining Raman spectroscopy of graphene because its peak positions are easily shifted due to the surface chemistry.
Scientific journal, English

Graphene etching controlled by atomic structures on the substrate surface
Takahiro Tsukamoto; Toshio Ogino
CARBON, PERGAMON-ELSEVIER SCIENCE LTD, 50, 2, 674-679, Feb. 2012, Peer-reviwed, We etched graphene on a sapphire (1-102) surface using the reaction between graphene and hydrogen catalyzed by metal nanoparticles. To investigate effects of the atomic structure of the sapphire substrate on graphene etching, we used sapphire substrate with as-polished, air-annealed, and step-ordered surfaces. We investigated the relationship between the atomic arrangement of sapphire and graphene etching and found that graphene is selectively etched in the [1-10-1] direction of sapphire. This indicates that atomic structure of the sapphire surface can be used as a template to control graphene etching. By combining the transfer method for graphene sheets grown on metal substrates with the present etching technique, graphene nanoribbons can be fabricated at a wafer level. (C) 2011 Elsevier Ltd. All rights reserved.
Scientific journal, English

Fabrication of Three-Dimensional Porous Alumina Microstructures Using Imprinting Method
Takahiro Tsukamoto; Toshio Ogino
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOC INC, 159, 4, C155-C159, 2012, Peer-reviwed, Three-dimensional porous alumina microstructures with vertically aligned nanopore array were self-assembled by anodic oxidation followed by an etching with phosphoric acid. By introducing micro-scaled hollow patterns to the initial aluminum surface by micro-contact imprinting, ordered microstructure arrays could be fabricated in large areas. Origin for the different etching rates of porous alumina membrane is believed to be the structural non-uniformity of the nanopore membranes: the porous alumina around the hollow areas introduced by the imprinting is stable against chemical etching due to the bent nanopores formed on the sidewall of the hollows. We can fabricate various porous alumina microstructure arrays in required positions by using this method and the shapes of the microstructures can be modified by regulating the applied voltage and selecting the intervals for the hollow areas. The present technique has a merit that three-dimensional building blocks with built-in nanopores can be fabricated whereas the conventional porous alumina has been a two-dimensional membrane. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.038204jes] All rights reserved.
Scientific journal, English

Control of Graphene Etching by Atomic Structures of the Supporting Substrate Surfaces
Takahiro Tsukamoto; Toshio Ogino
JOURNAL OF PHYSICAL CHEMISTRY C, AMER CHEMICAL SOC, 115, 17, 8580-8585, May 2011, Peer-reviwed, We attached single-layer graphene or few-layer graphene (FLG) on a sapphire (1-102) surface with well-ordered step/terrace structures and then etched them using catalytic nanoparticles. In the etching of FLG flakes, atomic steps can be utilized as guides or reflectors. In the case of single-layer graphene, the etching proceeds in a particular direction of a surface phase pattern on the terrace, and graphene nanoribbons are self-formed. The surface structures of the supporting substrate are good templates for graphene processing.
Scientific journal, English

'Graphene-on-insulator' fabricated on atomically controlled solid surfaces
T. Tsukamoto; T. Ogino
JOURNAL OF PHYSICS D-APPLIED PHYSICS, IOP PUBLISHING LTD, 43, 37, 374014-1-374014-6, Sep. 2010, Peer-reviwed, Graphene or few layer graphene (FLG) was attached on a single-crystalline sapphire surface on which a regularly ordered step/terrace structure was formed. The height of graphene from the substrate surface was observed to be about 0.35 nm, which is almost equal to the layer spacing of graphite. On the attached graphene or FLG surface, the step/terrace structure originating from the sapphire surface was clearly observed because the graphene flake tightly adhered to the sapphire surface. FLGs were etched by a reaction between carbon of the FLG and H(2) gas at 900 degrees C using Fe nanoparticles as catalysts. When a FLG flake is thick, the etching direction is subject to the crystallographic directions of graphene. As the FLG is thinner than 6 nm, strain induced on the FLG surface by the step/terrace structure of the substrate surface influences the etching direction, and etching along a buried step occurs when the Fe nanoparticle size is small. The etching directions of FLG can be controlled by the ordered atomic step arrangement on sapphire surfaces owing to the surface flatness and tight adhesion of graphene to the surface.
Scientific journal, English

Control of the spatial distribution of porous alumina micro-domes formed during anodic oxidation
Takahiro Tsukamoto; Toshio Ogino
ELECTROCHIMICA ACTA, PERGAMON-ELSEVIER SCIENCE LTD, 54, 20, 4712-4717, Aug. 2009, Peer-reviwed, We found that micro-domes of porous alumina are self-assembled during anodic oxidation of an aluminum plate. We investigated the effects of the morphology of the initial aluminum Surfaces on the formation of these micro-domes and found that the formation of micro-domes depends on the initial surface roughness of the substrate. We have also achieved spatial control over the distribution of these micro-domes through the use of artificial scratches on the initial surface. The origin of this control is the fact that micro-domes are preferentially formed inside hollow areas formed by the scratch. We investigated the inner structure of the micro-dome by separating it from the substrate. Inside the micro-domes, we observed nano-pore arrays similar to a porous alumina membrane, though the regularity of these pores is slightly worse than for the nano-pores around the micro-dome. These results indicate that the porous alumina micro-domes can be used as microscale nanoporous components. (C) 2009 Elsevier Ltd. All rights reserved.
Scientific journal, English

Morphology of Graphene on Step-Controlled Sapphire Surfaces
Takahiro Tsukamoto; Toshio Ogino
APPLIED PHYSICS EXPRESS, JAPAN SOCIETY APPLIED PHYSICS, 2, 7, 075502-1-075502-3, Jul. 2009, Peer-reviwed, Graphene attached on a sapphire surface with regularly ordered step-terrace structure was observed using atomic force microscopy (AFM). We found that graphene tightly adheres to a sapphire surface and the buried step structure on the sapphire surface was clearly observed on the graphene surface. Height of a single-layer graphene was estimated to be approximately 0.36 nm on sapphire surface, which is in good agreement with the theoretical height. These results indicate that sapphire is suitable for the substrate that supports graphene because we can obtain undistorted graphene that is tightly fixed on a substrate surface. (C) 2009 The Japan Society of Applied Physics
Scientific journal, English

Observation of Three Dimensional Micro-Scaled Structures Buries in Porous Alumia Layers Fabricated by Anodic Oxidation
Takahiro Tsukamoto; Takahide Oya; Toshio Ogino
e-J. Surf. Sci. Nanotech, 6, 147-151, 2008, Peer-reviwed
Scientific journal, English