Docter of Engineering, Nagoya University

Ad hoc network

Parallelized compiler

Parallel computer systems

Parallel processing

Parallel computer architecture

アドフォックネットワーック

並列化コンパイラ

コンピュータシステム

並列処理

計算機アーキテクチャ

Mar. 1974
Nagoya University, Graduate School, Division of Engineering, 電気及電子工学専攻

Efficient compilation for queue size constrained queue processors
Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
PARALLEL COMPUTING, ELSEVIER SCIENCE BV, 35, 4, 213-225, Apr. 2009, Queue computers use a FIFO data structure for data processing. The essential characteristics of a queue-based architecture excel at satisfying the demands of embedded systems, including compact instruction set, simple hardware logic, high parallelism, and low power consumption. The size of the queue is an important concern in the design of a realizable embedded queue processor. We introduce the relationship between parallelism, length of data dependency edges in data flow graphs and the queue utilization requirements. This paper presents a technique developed to make the compiler aware of the size of the queue register file and, thus, optimize the programs to effectively utilize the available hardware. The compiler examines the data flow graph of the programs and partitions it into clusters whenever it exceeds the queue limits of the target architecture. The presented algorithm deals with the two factors that affect the utilization of the queue, namely parallelism and the length of variables' reaching definitions. We analyze how the quality of the generated code is affected for SPEC CINT95 benchmark programs and different queue size configurations. Our results show that for reasonable queue sizes the compiler generates a code that is comparable to the code generated for infinite resources in terms of instruction count, static execution time, and instruction level parallelism. (C) 2008 Elsevier B.V. All rights reserved.
Scientific journal, English

A new code generation algorithm for 2-offset producer order queue computation model
Arquirnedes Canedo; Ben Abderazek; Masahiro Sowa
COMPUTER LANGUAGES SYSTEMS & STRUCTURES, PERGAMON-ELSEVIER SCIENCE LTD, 34, 4, 184-194, Dec. 2008, Peer-reviwed, Queue computing is an attractive alternative for the compulsive demand of high-performance architectures. Code generation for queue machines has some problems but the solutions have not been studied thoroughly. A new parallel queue computation model, 2-offset P-Code queue computation model, is presented together with a new code generation algorithm. The code generation algorithm takes leveled DAGs as input and produces 2-offset P-Code assembly. We also developed a queue compiler to evaluate the new algorithm and compiled a set of C language benchmark programs for the 2-offset P-Code. The queue compiler generates between 8.55% less instructions and 10.55% more instructions than an actual MIPS32 compiler for the compiled programs. (C) 2007 Elsevier Ltd. All rights reserved.
Scientific journal, English

Queue Programs Characterization using Performance Bounds
Arquimedes Canedo; Masahiro Sowa
International Workshop on Modern Science and Technology 2008, -, -, -, Nov. 2008
International conference proceedings, English

Construction of a SSA-based Queue Compiler
Yuki Nakanishi; Masahiro Sowa; Arquimedes Canedo
International Workshop on Modern Science and Technology 2008(IWMST2008), -, -, -, Nov. 2008
International conference proceedings, English

The QC-2 parallel Queue processor architecture
Ben A. Abderazek; Arquimedes Canedo; Tsutomu Yoshinaga; Masahiro Sowa
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, ACADEMIC PRESS INC ELSEVIER SCIENCE, 68, 2, 235-245, Feb. 2008, Peer-reviwed, Queue based instruction set architecture processor offers an attractive option in the design of embedded systems. In our previous work, we proposed a novel queue processor architecture as a starting point for hardware/software design space exploration for embedded applications. In this paper, we present a high performance 32-bit Synthesizable QueueCore (QC-2)-an improved and optimized version of the produced order parallel Queue processor (PQP), with single precision floating-point support. The QC-2 core also implements a novel technique used to extend immediate values and memory instruction offsets that were otherwise not representable because of bit-width constraints in the PQP processor.
A prototype implementation is produced by synthesizing the high-level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. (c) 2007 Elsevier Inc. All rights reserved.
Scientific journal, English

Queue Processor as Next Generation Fundamental ICT Infrastructure
Masahiro Sowa; Arquimedes Canedo
Kantaoui Forum TJASSST 2008, --, --, --, 2008, Peer-reviwed
International conference proceedings, English

Natural Instruction Level Parallelism-aware Compiler for High-Performance Embedded QueueCore
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
Journal of Embedded Computing, ==, ==, 2008, Peer-reviwed
Scientific journal, English

Compiling for Reduced Bit-Width Queue Processors
Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
Journal of Signal Processing Systems, 1939-8018, 2008, Peer-reviwed
Scientific journal, English

Quantitative evaluation of common subexpression elimination on queue machines
Arquimedes Canedo; Masahiro Sowa; Ben A. Abderazek
Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN, 25-30, 2008, Peer-reviwed, Queue computation model is a novel alternative for high performance architectures. Compiling for queue machines requires a different approach than compiling for traditional architectures. We have solved the problem of generating correct code with the queue compiler infrastructure. In this paper we introduce some problems encountered when optimizing code for queue machines. Common-subexpression elimination (CSE) is a widely used optimization to improve execution time. This paper makes a quantitative evaluation of how this optimization affects the characteristics of queue programs. We have found that in average, 28% of instructions are eliminated, and 15% of the critical path is reduced. We determine how enlarging the scope of compilation from expressions to basic blocks affects the distribution of offsetted instructions. © 2008 IEEE.
International conference proceedings, English

Mathematical model for multiobjective synthesis of NoC architectures
Ben A. Abderazek; Mushfiquzzaman Akanda; Tsutomu Yoshinaga; Masahiro Sowa
Proceedings of the International Conference on Parallel Processing Workshops, 1, 36-41, 2007, Peer-reviwed, Network-on-Chip (NoC) interconnections have been proposed to overcome the problems associated with long wires used in chip wide communications. They support asynchronous transfer of communication between cores within multicore systems-on-chips (MCSoCs). The design of such architectures is crucial for achieving high performance and energy efficient systems. However, the effectiveness of NoC based design depends on the adopted design methodology. Automatic design approach is highly desirable to increase system design productivity. This paper presents a new mathematical formulation for synthesizing application specific NoC architectures, such that the performance constraints are satisfied and the communication power consumption is minimized. © 2007 IEEE.
International conference proceedings, English

Queue register file optimization algorithm for QueueCore processor
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS, IEEE COMPUTER SOC, 169-176, 2007, Peer-reviwed, The queue computation model offers at? attractive alternative for high-performance embedded computing given its characteristics of short instructions and high instruction level parallelism. A queue-based processor uses a FIFO queue to read and write operands through hardware pointers located at the head and tail of the queue. Queue length is the number of elements stored between the head and the tail pointers during computations. We have found that 95% of the statements in integer applications require a queue length of less than 32 words. The remaining 5% requires larger queue length sizes up to 230 queue words. In this paper we propose a compiler technique to optimize the queue utilization for the hungry statements that require a large amount of queue. We show that for SPEC CINT95 benchmarks, our technique optimizes the queue length without decreasing parallelism. However our optimization has a penalty of a slight increase in code size.
International conference proceedings, English

Mathematical model for multiobjective synthesis of NoC architectures
Ben A. Abderazek; Mushfiquzzaman Akanda; Tsutomu Yoshinaga; Masahiro Sowa
Proceedings of the International Conference on Parallel Processing Workshops, 1, 36-41, 2007, Peer-reviwed, Network-on-Chip (NoC) interconnections have been proposed to overcome the problems associated with long wires used in chip wide communications. They support asynchronous transfer of communication between cores within multicore systems-on-chips (MCSoCs). The design of such architectures is crucial for achieving high performance and energy efficient systems. However, the effectiveness of NoC based design depends on the adopted design methodology. Automatic design approach is highly desirable to increase system design productivity. This paper presents a new mathematical formulation for synthesizing application specific NoC architectures, such that the performance constraints are satisfied and the communication power consumption is minimized. © 2007 IEEE.
International conference proceedings, English

Compiler Framework for an Embedded 32-bit Queue Processo
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
2007 International Conference on Convergence Information Technology (ICCIT¨07), 1793-1796, 2007, Peer-reviwed
International conference proceedings, English

Dual-Execution Mode Processor Architecture for embedded applications
Md. Musfiquzzaman Akanda; Ben Abderazek; Masahiro Sowa
Journal of Mobile Multimedia, 13, 4, 347-370, 2007, Peer-reviwed
Scientific journal, English

New code generation algorithm for QueueCore - An embedded processor with high ILP
Arquirnedes Canedo; Ben A. Abderazek; Masahiro Sowa
EIGHTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS, IEEE COMPUTER SOC, 185-192, 2007, Peer-reviwed, Modem architectures rely on exploiting parallelism found at the instruction level to achieve high performance. Aggressive ILP compilers expose high amounts of instruction level parallelism where, in some cases, the number of architected registers is not enough to hold the results of potential parallel instructions. This paper presents a new code generation scheme for the QueueCore, a 32-bit queue-based architecture capable of executing high amounts of ILP. QueueCore's instructions implicitly read their operands and write results. Compiling for the QueueCore requires that all instructions have at most one explicit operand represented as an offset calculated at compile-time. Additionally, the instructions must be scheduled in level-order manner The proposed algorithm successfully restricts all instructions to have at most one offset reference, it computes the offset values, and makes a level-order scheduling of the program. To evaluate the effectiveness of the new code generation scheme we developed a queue compiler and compiled a set of benchmark programs. Our results show that the code has more parallelism than optimized RISC code by factors ranging from 1.12 to 2.30. QueueCore's instruction set allows us to generate code about 40%-18% denser than optimized RISC code.
International conference proceedings, English

Queue register file optimization algorithm for QueueCore processor
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS, IEEE COMPUTER SOC, 169-176, 2007, Peer-reviwed, The queue computation model offers at? attractive alternative for high-performance embedded computing given its characteristics of short instructions and high instruction level parallelism. A queue-based processor uses a FIFO queue to read and write operands through hardware pointers located at the head and tail of the queue. Queue length is the number of elements stored between the head and the tail pointers during computations. We have found that 95% of the statements in integer applications require a queue length of less than 32 words. The remaining 5% requires larger queue length sizes up to 230 queue words. In this paper we propose a compiler technique to optimize the queue utilization for the hungry statements that require a large amount of queue. We show that for SPEC CINT95 benchmarks, our technique optimizes the queue length without decreasing parallelism. However our optimization has a penalty of a slight increase in code size.
International conference proceedings, English

Novel addressing method for aggregate types in queue processors
Teruhisa Yuki; Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
2007 International Conference on Convergence Information Technology, ICCIT 2007, 1793-1796, 2007, Peer-reviwed, Queue processors use a first-in first-out data structure to perform operations. Instructions implicitly reference their operands simplifying the design of the instruction set and the hardware complexity. Some access to memory require a computed address. A register-indirect addressing method introduces severe limitations in a queue processor by inserting false dependencies that limit the high parallelism capacity of such architectures. In this paper we propose a novel addressing method for queue processors that employ the queue for address calculation and memory access. We demonstrate that our new proposed method reduces the number of instructions by 6% and increases parallelism by 4% for a set of embedded applications. © 2007 IEEE.
International conference proceedings, English

An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
The 2007 IFIP International Conference on Embedded and Ubiquitous Computing EUC2007, 197-208, 2007, Peer-reviwed
International conference proceedings, English

Compiler Support for Code Size Reduction using a Queue-based Processo
Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
Transactions on High-Performance Embedded Architectures and Compilers, 2, 3, 153-169, 2007, Peer-reviwed
Scientific journal, English

Optimizing Reaching Definitions Overhead in Queue Processors
Yuuki Nakanisi; Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
Journal of Convergence Information technology, 2, 4, 36-40, 2007
Scientific journal, English

On the Design of a Dual-Execution Mode Processor: Architecture and Preliminary Evaluation
M. Akanda; B. A. Abderazek; M.Sowa
ISPA-2006 International Symposium on Parallel and Distributed Processing and Applications, 37-46, Dec. 2006, Peer-reviwed
International conference proceedings, English

High-level modeling and FPGA prototyping of produced order parallel queue processor core
Ben A. Abderazek; Tsutomu Yoshinaga; Masahiro Sowa
JOURNAL OF SUPERCOMPUTING, SPRINGER, 38, 1, 3-15, Oct. 2006, Peer-reviwed, Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base.
Scientific journal, English

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC
B. A. Abderazek; S. Kawata; T. Yoshinaga; M. Sowa
the 3rd Int. Workshop on Embedded Computing The 35th Int. Conf. on Parallel Processing, ICPP, pp217-229, Aug. 2006, Peer-reviwed
Scientific journal, English

Consumed-Order Queue Computation Model-New Model to Solve Drawbacks of Queue Computation Model-
Masahiro Sowa; Halcham Kutluk; B. A. Abderazek; Sotaro Kawata
The International Workshop on Modern Science and Technology 2006, 4, 1, 353-357, May 2006
International conference proceedings, English

A GCC-based Compiler for the Queue Register Processor (QRP-GCC)
Arquimedes Canedo; B. A. Abderazek; M.Sowa
The International Workshop on Modern Science and Technology 2006, 250-255, 2006, Peer-reviwed
International conference proceedings, English

Design and Architecture for an Embedded 32-bit QueueCore
B. A. Abderazek; S. Kawata; M. Sowa
the International Journal of Embedded Computing, Special issue on Single-Chip Multi-core Architectures and related research, 2, 2, pp. 191-205, 2006
Scientific journal, English

Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation
A. Markovskij; B. Abderazek; S. Kawata; M. Sowa
the 38th International Symposium on Microarchitecture, (MICRO-38,MSP7), 29-35, Dec. 2005, Peer-reviwed
International conference proceedings, English

Parallel queue processor architecture based on produced order computation model
M Sowa; BA Abderazek; T Yoshinaga
JOURNAL OF SUPERCOMPUTING, SPRINGER, 32, 3, 217-229, Jun. 2005, Peer-reviwed, This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a first-in-first-out (FIFO) circular queue-registers instead of random access registers. Datum is inserted in the queue-registers in produced order scheme and can be reused. We show that this feature has profound implications in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed.
Our performance evaluations show a significant performance improvement (e.g., 10 to 26% decrease in program size and 6 to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.
Scientific journal, English

An efficient dynamic switching mechanism (DSM) for hybrid processor architecture
AM Musfiquzzaman; BA Abderazek; S Kawata; M Sowa
EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, SPRINGER-VERLAG BERLIN, 3824, 77-86, 2005, Peer-reviwed, Increasing the processor resources usability and boosting processor compatibility and capability to support rnuiti-executiOns models in a single core are highly needed nowadays to benefit from the recent developments in electronics technology. This work introduces the conm,chsnjs. (DSM), which supports multicept of a dynamic switching instruction set execution models in a single and simple processor core. This is achieved dynamically by execution raode - switching scheme and a sources -results locations computing unit for a novel queue execution model and a well-known stack based execution model. The queue execution model is based on queue computation that uses queue-registers, a circular queue data structure, for operands and results manipulations and assigns queue words according to a single assignment rule. We present the nary evaluation results. We also describe the DSM target architecture.
Scientific journal, English

Modular design structure and high-level prototyping for novel embedded processor core
BA Abderazek; S Kawata; T Yoshinaga; M Sowa
EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, SPRINGER-VERLAG BERLIN, 3824, 340-349, 2005, In this research work, we present a high-level prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using modular design structure with control logic implemented as a set of communicating state machines, we show hardware emulation and optimizations results of a parallel queue proecssor architecture (QueueCore). We also show how to to fully exploit the capabilities of the designed QueueCore, while maintaining a common source base. From the evaluation results, we show that the QueueCore prototype fits on a single conventional FPGA device, thereby obviating the need to perform multi-chip partitioning which results in a loss of resource efficiency.
Scientific journal, English

Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters
V. Ta Qo; T. Yoshinaga; B. A. Abderazek; M. Sowa
IPSJ Transactions on Advanced Computing Systems, Information Processing Society of Japan (IPSJ), 46, SIG3(ACS8), 25-37, 2005, This paper proposes a middle-grain approach to construct hybrid MPI-OpenMP solutions for SMP clusters from an existing MPI algorithm. Experiments on different cluster platforms show that our solutions exceed the solutions that are based on the de-facto MPI model in most cases, and occasionally by as much as 40% of performance. We also prove an automatic outperformance of a thread-to-thread communication model over a traditional process-to-process communication model in hybrid solutions. In addition, the paper performs a detailed analysis on the hardware and software factors affecting the performance of MPI in comparison to hybrid models.
Scientific journal, English

Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme,
Ben Abderazek; Arsenji Markovski; Soichi Shigeta; Tsutom Yoshinaga; Masahiro Sowa
The 7th Perfomance Computaing and Grid in Asia Pacific Reagion(HPCAsia2004), Jul. 2004, Peer-reviwed
International conference proceedings, English

QJava:Inregrate Queue Computaional Model into Java
Soichi Shigeta; Li-Qiang Wang; N.Yagishita; Ben Abderazek; Tsutomu Yoshinaga; Masahiro Sowa
Proceedings of The Joint Japan-Tunisia worrkshop on ComputerSystem and Information Technology(JT-CSIT'04, pp60-65, 2004, Peer-reviwed
International conference proceedings, English

Queru Machine with Queue Extention Mechanism
Sotaro Kawata; Masahiro Sowa
COOL Chips Ⅶ, 2004, Peer-reviwed
International conference proceedings

On the design of a register queue based processor architecture (FaRM-rq)
BA Abderazek; S Shigeta; T Yoshinaga; M Sowa
PARALLEL AND DISTRIBUTED PROCESSING AND APPLICATIONS, PROCEEDINGS, SPRINGER-VERLAG BERLIN, 2745, 248-262, 2003, Peer-reviwed, We propose in this paper a processor architecture that supports multi instructions set through run time functional assignment algorithm (RUNFA). The above processor, which is named Functional Assignment Register Microprocessor (FaRM-rq) supports queue and register based instruction set architecture and functions into different modes: (1) R-mode (FRM) - when switched for register based instructions support, and (2) Q-mode (FQM) - when switched for Queue based instructions support. The entities share a common data path and may operate independently though not in parallel.
In FRM mode, the machine's shared storage unit (SSU) behaves as a conventional register file. However, in FQM mode, the system organizes the SSU access as a first-in-first-out latches, thus accesses concentrate around a small window and the addressing of registers is implicit trough the Queue head and tail pointers.
First, we present the novel aspects of the FaRM-rq(1) architecture. Then, we give the novel FQM fundamentals and the principles underlying the architecture.
Scientific journal, English

QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java
L. Wang; B. A. Abderazek; S. Shigeta; T. Yoshinaga; M. Sowa
Proceedings of International Technical Conference in Circuits/Systems, Computers and Communications, 900-903, 2003, Peer-reviwed
International conference proceedings, English

Proposal and Design of a Parallel Queue Processor Architecture(PQP)
Masahiro Sowa; Ben A. Abderazek; Soichi Shigeta; Tsutomu Yoshinaga
Proceedings of the 14th IASTED International Conference Parallel and Distributed Computing and Systems, 554-560, Nov. 2002, Peer-reviwed
International conference proceedings, English

"FARM Queue Mode: On a Practical Queue Execution Model(QEM)"
Ben,A.,Abderrazek; Kirilka Nikolova; Tutomu Yoshinaga; Masahiro Sowa
TIWSS'2001, Oct. 2001, Peer-reviwed
International conference proceedings, English

"Dynamic Crirical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing System"
Kirilka Nikolova; Ben Abderazek; Masahiro Sowa
ITC-CSCC'2001, 2, Jul. 2001, Peer-reviwed
International conference proceedings, English

"Access Route Control by Extended Key/Lock Scheme"
Shigeta,S; Shimizu,K; Sowa,M
International Journal of Computer Systems, Science and Engineering,CRL Publishing Ltd., 2001, Peer-reviwed
International conference proceedings, English

"Proposition and Evaluation of Parallelism-Independent Scheduling Algorithm for DAGs of Tasks with Non-Uniform Execution Times"
Kirilka Vassileva Nikolova; Atsusi Maeda; Masahiro Sowa
IEICE Transactions, E48-A, 6, 2001, Peer-reviwed
Scientific journal, English

"キー/ロック式の拡張によるアクセスルートコントロール"
繁田 聡一; 清水 謙多郎; 曽和 将容
情報処理学会論文誌, 42, 6, 2001, Peer-reviwed
Japanese

浅い束縛によるスコープ変数が存在する時の末尾再呼び出し
前田敦司; 曽和将容
情報処理学会論文誌, 40, 3, 2000, Peer-reviwed
Japanese

DRA: Dynamic Register Allocation for Accurate Parallel Instruction Issue and Dispatch in FARM Microprocessor
Ben Abdallah Abderrazek; Masahiro Sowa
The Third International Workshop on Advanced Parallel Processing Technologies APPT'99, October 19-21, Oct. 1999, Peer-reviwed
International conference proceedings, English

Design of a superscalar Processor Based on Queue Machine Computation Model
Shusuke Okamoto; Hitoshi Suzuki; Atusi Maeda; Masahiro Sowa
1999 IEEE Pacific Rim Conferences, Computers and Signal Processing（PACRIM 1999），August 22-24, Aug. 1999
International conference proceedings, English

A survey on the advances of diskI/O performance Metrics
Ben Abdallah Abderrazek; Mudar Sarem; Masahiro Sowa
International Conference on Robotics,Vision and Parallel Processing for Automation, Jul. 1999
International conference proceedings, English

Parallelism-Free Scheduling Method
Kirilka Nikolova; Atusi Maeda; Masahiro Sowa
ITC-CSCC'99（International Technical Conference on Circuits/Systems, Computers and Communications）, Jun. 1999
International conference proceedings, English

A Flexible Access Control Mechanism Based on the Key/Lock Scheme
Souichi Shigeta; Kenichi Shimizu; Shusuke Okamoto; Masahiro Sowa
ITC-CSCC'99（International Technical Conference on Circuits/Systems, Computers and Communications）, Jun. 1999
International conference proceedings, English

Relational Database Operations on Multi-processor with Program Controlled Cache Level Memory
Mitsuaki Nakasumi; Shusuke Okamoto; Masahiro Sowa
PDPTA'99 Conference , LasVegas, June28-July1, 1999
International conference proceedings, English

情報リテラシイ
立花康夫; 曽和将容; 春日秀雄
Japanese, Joint work, コロナ社, 2008

コンピュータアーキテクチャ
曽和将容
Japanese, Editor, コロナ社, 2006

コンピュータアーキテクチャ原理
曽和将容
Japanese, Editor, コロナ社, 1993

コンピュータ基礎工学
曽和将容; 柳瀬龍郎; 今井正治; 丹羽敏之
Japanese, Joint work, 昭晃堂, 1992

並列ＰＲＯＬＯＧコンピュータ
曽和将容
Japanese, Editor, 啓学出版, 1989

デ－タフロ－マシンと言語
曽和将容
Japanese, Editor, 昭晃堂, 1986

マイクロコンピュ－タＭＣ６８０９の考え方
曽和将容
Japanese, Editor, オ－ム社, 1982

トランジスタ回路を学ぶ人のために
曽和将容
Japanese, Joint work, オーム社, 1979

ディジタル回路の考え方
曽和将容; 清水賢資
Japanese, Joint work, オ－ム社, 1979

IEEE

ACM

情報処理学会

電子情報通信学会

日本ソフトウェア科学会

キュープロセッサおよびキュープロセッサによるデータ処理方法、およびキュープロセッサによるデータ処理プログラム
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コントロールフロー並列計算機方式
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