修士（工学）, 電気通信大学

博士（工学）, 電気通信大学

Internet Operation Technology

Computer network

Computer architecture

Parallel processing

Computer network

Computer architecture

並列処理

Informatics, Information networks

Informatics, Computer systems

Informatics, High-performance computing

Jan. 2024 - Present
The University of Electro-Communications, UEC-CSIRT, Associate Professor

Oct. 2023 - Present
The University of Electro-Communications, Graduate School of Informatics and Engineering, Associate Professor

Oct. 2023 - Present
The University of Electro-Communications, School of Informatics and Engineering, Associate Professor

Mar. 2021 - Present
The University of Electro-Communications, Information Technology Center, Associate Professor

Apr. 2018 - Mar. 2022
Tokyo University of Technology, School of Computer Science, Part-time lecturer

01 Mar. 2018 - 28 Feb. 2021
The University of Electro-Communications, Project Associate Professor

01 Sep. 2016 - 28 Feb. 2018
Hitotsubashi University, Research Associate

01 Apr. 2010 - 31 Aug. 2016
電気通信大学, 助教

01 Apr. 2012 - 31 Mar. 2013
The Ohio State University, Visiting Scholar

01 Apr. 2010 - 31 Mar. 2012
東京工科大学, 演習講師・実験講師

01 Apr. 2009 - 31 Mar. 2010
東京工科大学, 助教

01 Apr. 2007 - 31 Mar. 2009
東京工科大学, 助手

01 Apr. 2007 - 31 Mar. 2008
千葉商科大学, 非常勤講師

Apr. 2004 - Mar. 2007
電気通信大学, 電気通信学研究科, 情報工学専攻

Oct. 2022 - Mar. 2023
現地実行委員会, 情報処理学会・第８５回全国大会, Society

Nov. 2021
にいがたデジコングランプリ ＶＲコンテンツ部門 奨励賞
Others

AI History 1890-2090
Kaihei Hase; Syunji Yazaki
ACM SIGGRAPH Asia 2023 Art Gallery, ACM, 07 Dec. 2023
International conference proceedings

Evaluation of an Implementation Method for Pipeline Parallelism Distributed Deep Learning
Naoki Takisawa; Syunji Yazaki; Hiroaki Ishihata
IPSJ Journal, 63, 5, 1206-1215, May 2022, Peer-reviwed
Scientific journal, Japanese

Distributed Deep Learning of ResNet50 and VGG16 with Pipeline Parallelism
Naoki Takisawa; Syunji Yazaki; Hiroaki Ishihata
Proceedings of International Symposium on Computing and Networking (CANDAR) 2020, 130-136, Nov. 2020, Peer-reviwed
International conference proceedings, English

CUDA Offloading for Energy-Efficient and High-Frame-Rate Simulations using Tablets
Martinez-Noriega Edgar Josafat; Syunji Yazaki; Tetsu Narumi
Concurrency and Computation: Practice and Experience, John Wiley & Sons, Ltd., e5488, 1-14, Aug. 2019, Peer-reviwed
Scientific journal, English

Development of a web-based front-end environment to aid programming lectures on unix-like systems
Syunji Yazaki; Hideaki Tsuchiya; Hiroaki Ishihata
Journal of Information Processing, Information Processing Society of Japan, 26, 376-385, 01 Jan. 2018, Peer-reviwed, In this paper, we describe the details of the design and implementation of our Front-end Environment for Hands-on Activities (FEHA), which is a web-based programming environment. FEHA provides a programming environment on the web and utilizes existing Unix-like systems that equip a specialized programming environment as the build and runtime platform. FEHA controls the existing systems by using Secure SHell (SSH) and Rsync without any modification of the existing systems. We discuss a case study of FEHA in which it was applied to actual programming lectures at a university. In the lectures, 70% of the students completed registrations to use FEHA in about 3 min. In addition, they could understand how to use the FEHA and started submitting codes within several minutes after the registration. The case study shows that FEHA is able to provide a specialized programming environment for more than 100 students with a small amount of effort from the instructor and system administrator.
Scientific journal, English

FEHA: An Adaptive Web-based Front-end Environment to Support Hands-on Training in Parallel Programming
Syunji Yazaki; Takeshi Kikuchi; Hideaki Tsuchiya; Hiroaki Ishihata
Proceedings of The Future of Education 2016, LibreriaUniversitaria, 166-170, 30 Jun. 2016, Peer-reviwed
International conference proceedings, English

S3R: Automated Temperature Measurement in Small and Medium Sized Server Rooms by Using A Tiny Computer and Self-driving Robot
Syunji Yazaki; Hideaki Tsuchiya
Journal of Academic Computing and Networking, 国立大学法人情報系センター協議会, 19, 114-121, 28 Sep. 2015, Peer-reviwed
Scientific journal, Japanese

Visualization Tool for Development of Communication Algorithms and a Case Study Using the K Computer
Syunji Yazaki; Ryohei Suzuki; Fumiyoshi Shoji; Kenichi Miura; Hiroaki Ishihata
Proceedings of Future Computing 2015, 54-59, 22 Mar. 2015, Peer-reviwed
International conference proceedings, English

Consideration of Parallel Efficiency of Finite Difference Synthesis on Multiple Platforms
Takashi Hojo; Syunji Yazaki
Proceedings of International Workshop on Modern Science and Technology (IWMST2014), 343-349, 30 Oct. 2014, Peer-reviwed
International conference proceedings, English

Improving bandwidth utilization and fairness between tcp flows based on a machine-learning approach
Akihiro Shiozu; Syunji Yazaki; Koki Abe
IEEJ Transactions on Electronics, Information and Systems, Institute of Electrical Engineers of Japan, 133, 6, 1259-1268, 2013, Peer-reviwed, TCP, a current de facto standard transport-layer protocol of the Internet, cannot fully utilize the available bandwidth. Fairness between TCP flows is another important measure of TCP performance. We proposed a method for predicting the optimal size of the congestion window to avoid network congestion by using a machine learning approach. In this paper, based on the machine learning approach, we further improve the congestion algorithm with respect to utilization of the available bandwidth and fairness between TCP flows. The improvement includes bringing a size of the congestion windows closer to the optimum value, realizing fairness against congestion algorithms that aggressively use bandwidth, and adapting to the network where the available bandwidth abruptly changes. The proposed method is evaluated with respect to utilization of bandwidth and fairness between TCP flows including flows aggressively using bandwidth by simulation using NS-2.© 2013 The Institute of Electrical Engineers of Japan.
Scientific journal, English

An efficient all-to-all communication algorithm for mesh/torus networks
Syunji Yazaki; Haruyuki Takaue; Yuichiro Ajima; Toshiyuki Shimizu; Hiroaki Ishihata
Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012, 277-284, 2012, Peer-reviwed, An efficient all-to-all communication algorithm for torus and mesh networks, A2AT, was proposed. A2AT schedules message sending sequence so that all links are fully used by exploiting function of concurrent message transfer in the node. By using A2AT, the hop count of messages equals the maximum number of messages sharing a link in their routes for all message transfers. A2AT can therefore maintain synchronization without the need for phasing operation such as an MPI barrier. When the VOQ which is an ideal configuration for A2AT was used, communication times for mesh/torus network obtained by A2AT were roughly 1.20 and 1.09 times higher, on average, than those of the ideal times. When the networks had the minimum number of virtual channels and a small buffer, assuming a practical network, A2AT was able to reduce communication times by 12.5% and 36.0% compared with those of the conventional algorithm. When two controllers are used, A2AT reduced 28.2% and 55.7% communication time with those by A2AND on 15x15x15 (=3,375 nodes) mesh and torus networks respectively (18.6% and 44.8% in average). A2AT also reduced 15.1% and 41.9% of communication time with those by A2AND on the same mesh and torus networks respectively (14.4% and 37.5% in average) when six controllers are used. © 2012 IEEE.
International conference proceedings, English

Evaluation of Memory Recall Support System Using RFID Technology
Syunji Yazaki; Yuji Sato; Hiroshi Igaki; Nobuhiro Tsukie; Tohru Hoshi
Proc. of SICE Annual Conference 2011, 2862-2864, Sep. 2011, Peer-reviwed
International conference proceedings, English

2次元Mesh・Torusネットワーク上での最適全対全通信アルゴリズムの評価
高上治之; 矢崎俊志; 安島雄一郎; 清水俊幸; 石畑宏明
情報処理学会論文誌 コンピューティングシステム（ACS）, 4, 3, 36-46, May 2011, Peer-reviwed, 筆者らは Mesh・Torus ネットワーク上での全対全通信アルゴリズム A2AT を提案した．本論文では，A2AT の通信性能をフリットレベルのネットワークシミュレータを用いて評価した結果について報告する．現実的なモデルである，物理チャネルあたりのバーチャルチャネル数を 2 とした場合，予測値に対し平均約 1.09 倍の通信時間であり，既存の全対全通信アルゴリズムと比較して，約 12.3～48.0% 通信時間が低減され，ネットワークサイズが大きくなるほど優位であった．通信の開始時刻は各ノードでばらつきがある場合でも，ノード内でローカルな送受信の待ち合わせを行うことにより，各ノードでのわずかなタイミングのずれが全体の通信性能に影響を与えないことを示した．各ノードからの送信数を増やした場合は，送信数 1 のときと比べ，Mesh では平均約 18.8%，Torus では平均約 41.2% 通信時間が低減された．In this study, we evaluate the performance of a previously proposed all-to-all communication algorithm for torus and mesh networks (A2AT) by using a flit-level simulator. Under the realistic assumption that two virtual channels are used, the A2AT computation speed was 1.09 times the analytically predicted speed. And the A2AT communication time was 12.3% to 48.0% lower than that of an existing algorithm. Moreover, this difference increased with the network size. We show that the difference in the initialization times of the nodes had little effect on the communication performance. When the number of concurrent message transfers was set to more than one, A2AT communication time was reduced by 18.8% for the mesh network and by 41.2% for the torus network compared to that when the number of concurrent transfers was set to one.
Scientific journal, Japanese

メッセージフローに基づくネットワークシミュレータMFSの評価
矢崎俊志; 石畑宏明
情報処理学会論文誌 コンピューティングシステム（ACS）, 4, 3, 47-55, May 2011, Peer-reviwed, 本論文では，筆者らが通信アルゴリズムの評価を目的として提案したフローベースシミュレータ Message Flow Simulator（MFS） の，より汎用的な利用可能性を示すため，既存のパケットベースシミュレータ Booksim を用いて様々なネットワークトポロジと通信パターンで MFS を比較評価した結果を述べる．筆者らはこれまで，MFS がパケットベースシミュレータ BigSimulator より短時間で全対全通信アルゴリズムを評価可能であることを示した．また，メッセージが相互結合網を通過する時間のみを評価可能な Booksim を用いて，Fattree ネットワーク上のランダム通信シミュレーションによる比較評価を行ってきた．本論文では新たに MFS と Booksim のシミュレーション結果の差がスイッチで行われるアービトレーションの影響により生じることを示した．このことから，通信の平均ホップ数が少ないトポロジのネットワーク評価や，近距離のノード通信を頻繁に行う並列プログラムの通信シミュレーションに MFS が利用できる可能性を示した．1 万ノード以上の大規模なネットワークについて，全ノードが 10 パケットをランダムな宛先に送るシミュレーションを実行した．このとき，MFS は Booksim の 1～2% の実行時間とメモリ使用量でシミュレーションを実行した．This paper describes evaluation results of Message Flow Simulator (MFS) to show capabilities of application of MFS. MFS is a flow-based network simulator for large-scale parallel computer. We previously showed that MFS performed simulation of all-to-all communication algorithms faster than BigSimulator which is a packet-based network simulator. We also compared evaluation results of communication time estimated by MFS and Booksim which is a packet-based network simulator. In the paper, we show that MFS gives different result with Booksim due to effect of the arbitration in the router. From this result, we find that MFS provides better results when many messages are communicated in low hop count or average hop count in networks is low. MFS performs simulation with less run-time and memory usage when the number of nodes is over 10,000. Run-time and memory usage of MFS were from 1% to 2% by those of Booksim.
Scientific journal, Japanese

Memory Recall Support System Using RFID Technology
Syunji Yazaki; Nobuhiro Tsukie; Toshio Matsunaga
Proc. of IWMST2010, 133-137, Sep. 2010, Peer-reviwed
International conference proceedings

Evaluation of Activity Level of Daily Life Based on Heart Rate and Acceleration
Syunji Yazaki; Toshio Matsunaga
Proc. of SICE Annual Conference 2010, 1002-1005, Aug. 2010, Peer-reviwed
International conference proceedings, English

2次元Meshネットワーク・Torusネットワーク上での最適全対全通信アルゴリズム
高上治之; 矢崎俊志; 安島雄一郎; 清水俊幸; 石畑宏明
情報処理学会論文誌 コンピューティングシステム（ACS）, 情報処理学会, 3, 2, 88-98, Jun. 2010, Peer-reviwed, 本論文では，各ノードは同時に複数のメッセージを送受信可能なモデルを前提とした，2 次元 Mesh ネットワーク・Torus ネットワーク上での全対全通信アルゴリズムを提案する．提案するアルゴリズムでは，各ノードは，複数のメッセージを同時に送信する方式をとっており，Mesh ネットワークでは，同時に 2 つのメッセージを送信することにより，Torus ネットワークでは，同時に 4 つのメッセージを送信することによりネットワークのバイセクションバンド幅を最大限に引き出すようにスケジューリングしている．本方式での通信時間は，2 次元 Mesh ネットワーク・Torus ネットワーク上での理論的下限を達成していることを示す．In this paper, we present an optimal all-to-all communication algorithm for a 2D mesh/torus network. The proposed algorithm ensures full utilization of the network link bisection bandwidth without the need for split-phase operation, which are used in previously proposed algorithm, provided each node can transfer several messages concurrently. We show the proposed alogrithms acheives the theoretical lower bound time of all-to-all communicaiton in both a 2D mesh with two concurrent message transfers and a 2D torus with four concurrent message transfers.
Scientific journal, Japanese

通信アルゴリズム評価用メッセージフローシミュレータの開発
矢崎俊志; 石畑宏明
情報処理学会論文誌 コンピューティングシステム（ACS）, 3, 2, 76-87, Jun. 2010, Peer-reviwed
Scientific journal, Japanese

Message Flow Simulator for Evaluating Communication Algorithms
Syunji Yazaki; Hiroaki Ishihata
Proceedings of The Ninth IASTED international Conference on Parallel and Distributed Computing and Networks 2010, 291-298, Feb. 2010, Peer-reviwed
International conference proceedings, English

Implementation of Personalized Web Bulletin Board System Based on Student Profiles, Career Plans, and Subject Registration
Syunji Yazaki; Kent Terasawa; Nobuhiro Tsukie; Toshio Matsunaga
Proceedings of International Symposium on Tangible Software Engineering Education (STANS2009), 157-164, Oct. 2009, Peer-reviwed
International conference proceedings, English

An Approach to Practical Software Engineering Education in Nippon Engineering College
Nobuhiro Tsukie; Hiroyuki Maruyama; Syunji Yazaki; Akio Takashima; Hiroyuki Kameda; Taichi Nakamura
Proceedings of International Symposium on Tangible Software Engineering Education (STANS2009), 59-65, Oct. 2009, Peer-reviwed
International conference proceedings, English

A Proposal of Portable Life Supporting System Using Wireless Wearable Biosensor for Elderly People
Syunji Yazaki; Matsuanga
Proceedings of ICCAS-SICE2009 Joint Conference, 2763-2768, Aug. 2009, Peer-reviwed
International conference proceedings, English

VLSI Design of Karatsuba Integer Multipliers and Its Evaluation
Syunji Yazaki; Koki Abe
ELECTRONICS AND COMMUNICATIONS IN JAPAN, SCRIPTA TECHNICA-JOHN WILEY & SONS, 92, 4, 9-20, Apr. 2009, Peer-reviwed, Multidigit multiplication is widely used for various applications in recent years, including numerical calculation, chaos arithmetic, and primality testing. Systems with high performance and low energy Consumption are demanded, especially for image processing and communications with cryptography using chaos. Karatsuba algorithm with computational complexity of O(n(1.58)) has been employed in software For multiplication of hundreds to thousands of bits, where n stands for bit-length of, operands. In this paper, hardware design of multidigit integer multiplication based on Karatsuba algorithm is described and its VLSI realization is evaluated in terms of the cost, performance, and energy consumption. We present two design choices of the Karatsuba hardware: RKM (Recursive Karatsuba Multiplier) and IKM (Iterative Karatsuba Multiplier). We found that RKM has less area cost than WTM (Wallace Tree Multiplier) for bit-length larger than 2(9) with area cost of 30 mm(2). Critical path delay of RKM is always larger than that of WTM. Therefore, we should use WTM as combinational circuits for IKM to have better cost performance. We also found that a version of IKM using 0.18 pm process can perform 1024-bit rnultiplications 30 times faster than software at the area cost of 10.9 mm(2). Energy for the Computation by the IKM version Was found to be nearly 1/600 of that consumed by general-purpose processor which executes the software. The results obtained by this study will help system designers for applications requiring multidigit multiplication to select design alternatives including ASIC realization. (C) 2009 Wiley Periodicals, Inc. Electron Comm Jpn, 92(4): 9-20, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecj.10086
Scientific journal, English

Karatsuba整数乗算器のVLSI設計と評価
矢崎俊志; 阿部公輝
電気学会論文誌C, The Institute of Electrical Engineers of Japan, 128, 2, 220-230, Feb. 2008, Peer-reviwed, Multi-digit multiplication is widely used for various applications in recent years, including numerical calculation, chaos arithmetic, primality testing. Systems with high performance and low energy consumption are demanded, especially for image processing and communications with cryptography using chaos. Karatsuba algorithm with computational complexity of O(n^1.58) has been employed in software for multiplication of hundreds to thousands bits, where n stands for bit length of operands. In this paper, hardware design of multi-digit integer multiplication based on Karatsuba algorithm is described and its VLSI realization is evaluated in terms of the cost, performance, and energy consumption. We present two design choices of the Karatsuba hardware: RKM (Recursive Karatsuba Multiplier) and IKM (Iterative Karatsuba Multiplier). We found that RKM has less area cost than WTM (Wallace Tree Multiplier) for bit length larger than 2⁹ with area cost of 30mm². Critical path delay of RKM is always larger than that of WTM. Therefore, we should use WTM as combinational circuits for IKM to have better cost performance. We also found that a version of IKM using 0.18μm process can perform 1024-bit multiplications 30 times faster than software at the area cost of 10.9mm². Energy for the computation by the IKM version was found to be nearly 1/600 of that consumed by general purpose processor which executes the software. The results obtained by this study will help system designers for applications requiring multi-digit multiplication to select design alternatives including ASIC realization.
Scientific journal, Japanese

A Proposal of Abnormal Condition Detection System for Elderly People Using Wireless Wearable Biosensor
Syunji Yazaki; Toshio Matsunaga
2008 PROCEEDINGS OF SICE ANNUAL CONFERENCE, VOLS 1-7, IEEE, 2149-2153, 2008, Peer-reviwed
International conference proceedings, English

VLSI design of iterative Karatsuba multiplier and its evaluation
Syunji Yazaki; Koki Abe
PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS, ACTA PRESS ANAHEIM, 313-+, 2006, Peer-reviwed, Multi-digit multiplication is widely used for various applications in recent years, including numerical calculation, chaos arithmetic, primality testing. Systems with high performance and low energy consumption are demanded, especially for image processing and communications with cryptography using chaos. In this paper, hardware design of multi-digit integer multiplication is described and its VLSI realization is evaluated in terms of the cost and performance. A version of Karatsuba hardware using 0.18 mu m process can perform 512-bit multiplications 30 times faster than software at the area cost of 6.91 mm(2). Computation energy was found to be nearly 10(-3) of that consumed by general purpose processor which executes the software version. The results obtained by this study will help system designers for applications requiring multi-digit multiplication to select design alternatives including ASIC realization.
International conference proceedings, English

VLSI Implementation of Karatsuba Algorithm and Its Evaluation
Syunji Yazaki; Koki Abe
Proceedings of The International Workshop on Modern Science and Technology in 2006, 378-383, 2006, Peer-reviwed
International conference proceedings, English

An Optimum Design of FFT Multi-Digit Multiplier and Its VLSI Implementation
Syunji Yazaki; Koki Abe
Bulletin of the University of Electro-Communications, 18, 1,2, 39-46, Jan. 2006, Peer-reviwed
Research institution, English

FFT多倍長乗算器のVLSI設計
矢崎俊志; 阿部公輝
日本応用数理学会論文誌, 15, 3, 385-401, 2005, Peer-reviwed
Scientific journal, Japanese

v.Connect : A Singing Synthesis System Enabling Users to Control Vocal Tones
Makoto Ogawa; Syunji Yazaki; Koki Abe
Since the release of Hatsune Miku, interets in singing synthesis increase. For example, a singing synthesis system, UTAU, has been developed as a freeware. Most of these systems, however, lack of the function that users can mix vocal tones at any times. Controling tonal changes in singing requires a large amount of time and data for synthesis. We have developed a singing synthesis system, v.Connect, which connects corresponding phonemes with a time-stretching function to enable users to control tonal changes in singing by specifying the rate of voice morphing. The system processes voice signals with WORLD, a voice synthesis and analysis system, and uses corpora of various tonal voices consisting of Mel cepstra and excitation signals compressed by Vorbis. We constructed a corpus, "Namine Ritsu Connect", using the proposed method. It was found that the size of the corpus was two times larger than that of raw waves, and that synthesis from the corpus was 1.7 to 2.2 times faster than that from raw waves. Degradation caused by compression was not sensed subjectively., Information Processing Society of Japan (IPSJ), 27 Jan. 2012, IPSJ SIG Notes, 2012, 10, 1-7, Japanese, 110009753262, AN10442647

メッセージフローに基づくネットワークシミュレータMFSの評価—An Evaluation of Message-flow-based Network Simulator
矢崎 俊志; 石畑 宏明
東京 : 情報処理学会, Oct. 2011, 情報処理学会論文誌 論文誌トランザクション, 2011年度, 1, 47-55, Japanese, 1882-7772, 170000063911, AN00116647

C-022 A Low-power Access Method for Set-associative Cache Using Characteristics of Memory Access Instructions
Aita Yasuo; Okabe Sho; Yazaki Syunji; Abe Koki
Forum on Information Technology, 07 Sep. 2011, 情報科学技術フォーラム講演論文集, 10, 1, 445-446, Japanese, 110009623354, AA1242354X

F-028 An Automated Filtering Method for Web Contents
Ikeda Masakuni; Yazaki Syunji; Abe Koki
Forum on Information Technology, 07 Sep. 2011, 情報科学技術フォーラム講演論文集, 10, 2, 475-478, Japanese, 110009623189, AA1242354X

An Evaluation of Message-flow-based Network Simulator
矢崎 俊志; 石畑 宏明
11 Jan. 2011, ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集, 2011, 1-9, Japanese, 170000063911

Evaluation of Optimal All-to-All Communication Algorithm on 2-dimensional Mesh Network and Torus Network
高上 治之; 矢崎 俊志; 安島 雄一郎; 清水 俊幸; 石畑 宏明
11 Jan. 2011, ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集, 2011, 33-41, Japanese, 170000063916

Evaluation of Optimal All-to-All Communication Algorithm on Mesh Network and Torus Network
TAKAUE HARUYUKI; YAZAKI SYUNJI; AJIMA YUICHIRO; SHIMIZU TOSHIYUKI; ISHIHATA HIROAKI
本論文では，筆者らが提案した Mesh・Torus ネットワーク上での全対全通信アルゴリズム A2AT について，フリットレベルのネットワークシミュレータである Booksim を用いて通信性能の評価について報告する．A2AT ではバーチャルチャネルを宛先ノード数分だけ用意し，全メッセージ間で公平なアービトレーションとした場合，理論値に対し，Torus では平均約 0.97 倍，Mesh では平均約 1.25 倍の通信時間がかかった．一方，より現実のマシンに近いパラメータのケースでは，理論値に対し平均約 1.11 倍の通信時間であった．既存の全対全通信アルゴリズム A2AND と比較すると，差が 1.29 倍～ 1.90 倍とネットワークの構成が大きくなるほど，差が広がり A2AT の方が優位であった．各ノードからの送信数を 2，4 と増やした場合でも，送信数 1 のときと比べ，Mesh では平均約 1.13 倍早く，Torus では平均約 1.35 倍早く通信が完了した．We evaluate the performance of previously proposed all-to-all communication algorithm (A2AT) by using Booksim, a flit level simulator. A2AT attains 0.97 to 1.25 times of theoretical communication time under nearly ideal condition that the routers in the simulation model have enough number of virtual channels. The case when the number of virtual channels is limited to two and the routers have adequate size of buffer, this is more practical condition in actual system, A2AT achieves 1.11 times of theoretical communication time. We also show that A2AT is 1.29 to 1.90 times better than existing algorithm and its difference increases when the network size becomes large. When the numbers of concurrent message transfer are 2 and 4, A2AT performs 1.13 to 1.35 times faster than that of 1., 情報処理学会, 27 Jul. 2010, 研究報告ハイパフォーマンスコンピューティング（HPC）, 2010, 15, 1-8, Japanese, 0919-6072, 110007995503, AN10463942

B-027 Performance Comparison of All-to-All Communication Algorithms on 2-dimensional Mesh Network
Takaue Haruyuki; Suzuki Yutaro; Yazaki Syunji; Ishihata Hiroaki
Forum on Information Technology, 20 Aug. 2009, 情報科学技術フォーラム講演論文集, 8, 1, 417-418, Japanese, 110008100251, AA1242354X

B-028 A Communication Network Simulator Based on Message Flows and I'ts Parallelization
Suzuki Yutaro; Takaue Haruyuki; Yazaki Syunji; Ishihata Hiroaki
Forum on Information Technology, 20 Aug. 2009, 情報科学技術フォーラム講演論文集, 8, 1, 419-420, Japanese, 110008100252, AA1242354X

An Implementation of Watermarking Algorithms for Mobile Phone and Its Evaluation
KOSEKI Yosuke; YAZAKI Syunji; MATSUNAGA Toshio; TSUKIE Nobuhiro
10 Mar. 2009, 全国大会講演論文集, 71, 417-418, Japanese, 110007499491, AN00349328

Development and Evaluation of User Adaptive Interface Supporting a Choice of Menu-buttons on the Mobile-Phone
TSUKIE Nobuhiro; MORITOU Eiichirou; YAZAKI Syunji; MATSUNAGA Toshio
10 Mar. 2009, 全国大会講演論文集, 71, 3-4, Japanese, 110007505520, AN00349328

Comfortable Life Supporting System for Elderly People Using Biosensing Technology and RFID
YAZAKI Syunji; MATSUNAGA Toshio; TSUKIE Nobuhiro
05 Mar. 2009, 電気学会研究会資料. IIS, 産業システム情報化研究会, 2009, 12, 11-16, Japanese, 80020202058, AN10220703

Collision Prediction by Using a Video Image of a Single Camera in a Car
WATANABE Genki; YAZAKI Syunji; MATHUNAGA Toshio
13 Mar. 2008, 全国大会講演論文集, 70, 325-326, Japanese, 110006866766, AN00349328

An Optimum Implementation of FFT Multiplier
YAZAKI Syunji; ABE Koki
FFT can be useful to calculate the multi-digit multiplication used for cryptography. Here, we describe an optimum hardware implementation of an FFT multiplier. Because the required precision depends on the number of digits to be calculated, the least bit length of the floating point number varies. We performed an experimental error analysis and implemented an FFT multiplier using an optimum data representation obtained by the analysis. We found from the implementation that our optimized FFT multiplier could reduce the area by 1/3 and improve the performance 1.3 times, compared to the 64-bit IEEE754 representation in multiplying hexadecimal values of 2^<11> digits., Information Processing Society of Japan (IPSJ), 02 Dec. 2004, 情報処理学会研究報告システムLSI設計技術（SLDM）, 2004, 122, 233-238, Japanese, 0919-6072, 110002695808, AA11451459

An Optimum Implementation of FFT Multiplier
YAZAKI Syunji; ABE Koki
FFT can be useful to calculate the multi-digit multiplication used for cryptography. Here, we describe an optimum hardware implementation of an FFT multiplier. Because the required precision depends on the number of digits to be calculated, the least bit length of the floating point number varies. We performed an experimental error analysis and implemented an FFT multiplier using an optimum data representation obtained by the analysis. We found from the implementation that our optimized FFT multiplier could reduce the area by 1/3 and improve the performance 1.3 times, compared to the 64-bit IEEE754 representation in multiplying hexadecimal values of 2^<11> digits., The Institute of Electronics, Information and Communication Engineers, 02 Dec. 2004, IEICE technical report. Dependable computing, 103, 482, 163-168, Japanese, 0913-5685, 110003204346, AA11645397

Hardware Design and Evaluation of Multidigit FFT multiplier and Its VLSI Implementation
YASAKI Syunji; ABE Koki
Multiplication of multidigit numbers ranging thousands digits is required in many applications such as calculation of π, cipher, etc. Multidigit multiplication is efficiently performed by FFT algorithms. In this paper we present a hardware design of FFT multiplication. First, we examine several alternatives in organizing the multiplier based on their costs required and performance obtained. Next we demonstrate the usefulness of the hardware implementation by comparing the performance with software implementation. We further present a VLSI realization of a small scale FFT multiplier on a 2.8mm square chip using CMOS 0.18μm technology, using a 16 bit data representation in floating point multiplication. The FFT multiplier using 64 bit data representation which enables 216 multiplication was found t,o be implemented on a chip of about 10mm square., The Institute of Electronics, Information and Communication Engineers, 28 Nov. 2003, Technical report of IEICE. VLD, 103, 476, 253-258, Japanese, 0913-5685, 110003294254, AN10013323

Hardware Design and Evaluation of Multidigit FFT multiplier and Its VLSI Implementation
YASAKI Syunji; ABE Koki
Multiplication of multidigit numbers ranging thousands digits is reauired in many applications such as calculation of π, cipher, etc. Multidigit multiplication is efficiently performed by FFT algorithms. In this paper wepresent a hardware design of FFT multiplication. First, we examine several alternatives in organizing the multiplier based on their costs required and performance obtained. Next we demonstrate the usefulness of the hardware implementation by comparing the performance with software implementation. We further present a VLSI realization of a small scale FFT multiplier on a 2.8mm square chip using CMOS 0.18μm technology, using a 16 bit data reoresentation in floating point multiplication. The FFT multiplier using 64 bit data representation which enables 2^<16> multiplication was found to be implemented on a chip of about 10mm square., Information Processing Society of Japan (IPSJ), 27 Nov. 2003, 情報処理学会研究報告システムLSI設計技術（SLDM）, 2003, 120, 283-288, Japanese, 0919-6072, 110002687639, AA11451459

An Implementation Method of a Processor with a Multiple Precision Arithmetic Feature : Multiplier
Tsukie Nobuhiro; Yazaki Syunji; Matsunaga Toshio
The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2002, Proceedings of the IEICE General Conference, 2002, 107-107, Japanese, 110003496298, AN10471452

電気通信大学におけるサイバーセキュリティ教育
矢崎俊志
Public discourse, 数理・データサイエンス・AI教育強化拠点コンソーシアム 第8回ワークショップ「データサイエンスにおけるサイバーセキュリティ教育事例」
22 Mar. 2024

Temperature and humidity controls of Machine rooms of UEC
Hideaki Tsuchiya; Kunihiro Onishi; Kazuhiro Ishii; Akio Yamaguchi; Shuji Hattori; Syunji Yazaki; Masayuki Takata
Oral presentation, Japanese, 第27回学術情報処理研究集会
06 Sep. 2023
05 Sep. 2023- 06 Sep. 2023

UEC-BB: Open BugBounty on Campus Contributed by student at The University of Electro-Communications
YAZAKI Syunji; YAMAGUCHI Akio; WATANABE Key; TSUCHIYA Hideaki
Oral presentation, Japanese, 第27回学術情報処理研究集会
05 Sep. 2023
05 Sep. 2023- 06 Sep. 2023

Performance Evaluation of IEEE 802.11ah Wi-Fi HaLow at The University of Electro-Communications
YAZAKI Syunji; OGAWA Hirohide; TAKAYAMA Daiki; MARUYAMA Masanori; ONISHI Kunihiro; ISHII Kazuhiro; YAMAGUCHI Akio; HATTORI Shuji; TSUCHIYA Hideaki; TAKATA Masayuki
Oral presentation, Japanese, 第27回学術情報処理研究集会
05 Sep. 2023
05 Sep. 2023- 06 Sep. 2023

VR-HMD をメディアとする芸術作品におけるゾートロープを用いた演出
長谷 海平; 矢崎 俊志; 柴崎 幸次; 関口 敦仁
Poster presentation, Japanese, NICOGRAPH 2022, 芸術科学会
04 Nov. 2022

仮想空間での映像表現展
長谷 海平; 矢崎 俊志
Oral presentation, Japanese, 日本映像学会, Invited, Domestic conference
17 Sep. 2022

作品 “In Front of the Horizont (Cycloroma)”
長谷 海平; 矢崎 俊志; 柴崎 幸次; 関口 敦仁
Oral presentation, Japanese, 第27回日本バーチャルリアリティ学会大会論文集, Domestic conference
12 Sep. 2022

A Study of Sound Expression Techniques in XR
Kaihei HASE; Syunji Yazaki; Koji Shibazaki; Atsuhito Sekiguchi
Oral presentation, Japanese, Technical Meeting on Perception Information, Domestic conference
21 Aug. 2021

Virtual Reality における散策空間
長谷 海平; 矢崎 俊志
Oral presentation, Japanese, 環境芸術学会2021年度春季研究発表大会, Domestic conference
16 May 2021

パイプライン並列分散深層学習の一実装手法の提案
滝澤 尚輝; 矢崎 俊志; 石畑 宏明
Oral presentation, Japanese, 情報処理研究会報告 第 179 回 HPC 研究会, 情報処理学会 HPC 研究会, Domestic conference
May 2021

UEC Bug Bounty 2019: 電気通信大学における学内 Bug Bounty Program の実施
矢崎 俊志; 山口 昭男; 渡辺 圭; 鈴木 健一郎; 土屋 英亮
Oral presentation, Japanese, 大学ICT推進協議会2020年度 年次大会, Domestic conference
Dec. 2020

Construction and operation of programming environment in a laboratory of computer science
石畑 宏明; 矢崎 俊志
Oral presentation, Japanese, 電子情報通信学会技術報告 教育工学研究会, Domestic conference
12 Oct. 2019

ディープラーニングを用いた楽音認識
内藤 結貴; 矢崎 俊志; 石畑 宏明
Oral presentation, Japanese, 電子情報通信学会技術研究報告 マルチメディア情報ハイディング・エンリッチメント研究会 (EMM)
05 Mar. 2018

クラスタリングを用いた並列コンピュータネットワークトラフィック特徴抽出の提案
菅生 伸也; 矢崎 俊志; 石畑 宏明
Oral presentation, Japanese, 第 77 回 情報処理学会 全国大会, Domestic conference
17 Mar. 2015

ハンズオン講義・デモンストレーションを支援する計算機システム向けフロントエンド環境の提案 -並列処理の講義への適用-
矢崎 俊志; 石畑 宏明
Oral presentation, Japanese, 情報処理研究会報告 第 148 回 HPC 研究会, 情報処理学会 HPC 研究会, 大分, Domestic conference
02 Mar. 2015

有限差分法によるシンセサイザの実装における並列化効率の検討
北條 崇; 矢崎 俊志
Oral presentation, Japanese, 電子情報通信学会 2014 年総合大会, 新潟大学, Domestic conference
Mar. 2014

電気通信大学のシステム運用の取り組みについて
桃井恵美; 矢崎俊志
Oral presentation, Japanese, 第23回情報処理センター等担当者技術研究会 報告集,第23回情報処理センター等担当者技術研究会
Aug. 2012

電気通信大学の全学包括ライセンスサービスへの取り組みと導入効果
服部修二; 桃井恵美; 山口昭男; 大西邦弘; 石井和広; 岡野豊; 才木良治; 矢崎俊志; 高田昌之; 土屋英亮; 桑田正行
Oral presentation, Japanese, 第23回情報処理センター等担当者技術研究会 報告集,第23回情報処理センター等担当者技術研究会
Aug. 2012

v.Connect：ユーザが声色操作可能な歌声合成器
小川真; 矢崎俊志; 阿部公輝
Oral presentation, Japanese, 情報処理学会研究会報告,第94回音楽情報科学研究会
Feb. 2012

FUNaVi-Key: 制御された意外性のある検索システム
船曳崇也; 矢崎俊志; 阿部公輝
Oral presentation, Japanese, エンタテインメントコンピューティング2011 (EC2011),エンタテインメントコンピューティング2011 (EC2011)
Oct. 2011

コンテンツフィルタリングの自動化手法
池田匡邦; 矢崎俊志; 阿部公輝
Oral presentation, Japanese, 第8回情報科学技術フォーラム (FIT2011),第8回情報科学技術フォーラム (FIT2011)
Sep. 2011

メモリアクセス命令の特徴を利用したセットアソシアティブキャッシュの低電力アクセス手法
会田康男; 岡部翔; 矢崎俊志; 阿部公輝
Oral presentation, Japanese, 第8回情報科学技術フォーラム (FIT2011),第8回情報科学技術フォーラム (FIT2011)
Sep. 2011

Caterpillar GC: 旧世代領域の分割を行うインクリメンタルな世代別実時間ごみ集め
尾沢崇; 矢崎俊志; 阿部公輝
Oral presentation, Japanese, 第8回情報科学技術フォーラム (FIT2011),第8回情報科学技術フォーラム (FIT2011)
Sep. 2011

2次元Mesh・Torusネットワーク上での最適全対全通信アルゴリズムの評価
高上治之; 矢崎俊志; 安島雄一郎; 清水俊幸; 石畑宏明
Public symposium, Japanese, 2011年ハイパフォーマンスコンピューティングと計算科学シンポジウム (HPCS2011), 情報処理学会, 茨城県つくば市
Jan. 2011

メッセージフローに基づくネットワークシミュレータMFSの評価
矢崎俊志; 石畑宏明
Public symposium, Japanese, 2011年ハイパフォーマンスコンピューティングと計算科学シンポジウム (HPCS2011), 情報処理学会, 茨城県つくば市
Jan. 2011

RFIDを用いた移動履歴に基づく想起支援システム
佐藤 悠士; 井垣 宏; 矢崎俊志; 月江 伸弘; 星 徹
Oral presentation, Japanese, 計測自動制御学会システムインテグレーション部門講演(SI2010),計測自動制御学会システムインテグレーション部門講演会(SI2010)
Dec. 2010

Mesh・Torusネットワーク上での最適全対全通信アルゴリズムの評価
高上浩之; 矢崎俊志; 安島雄一郎; 清水俊幸; 石畑宏明
Oral presentation, Japanese, 情報処理学会,SWoPP2010金沢，HPC研究会
Aug. 2010

心拍数と加速度に基づく緊張状態を考慮した人の活動量評価手法の提案
矢崎俊志; 松永俊雄
Oral presentation, Japanese, 電気学会,平成22年電気学会産業応用部門大会
Aug. 2010

2次元Meshネットワーク・Torusネットワーク上での最適全対全通信アルゴリズム
高上治之; 矢崎俊志; 安島雄一郎; 清水俊幸; 石畑宏明
Public symposium, Japanese, 2010年ハイパフォーマンスコンピューティングと計算科学シンポジウム (HPCS2010), 情報処理学会, 東京
Jan. 2010

通信アルゴリズム評価用メッセージフローシミュレータの開発
矢崎俊志; 石畑宏明
Public symposium, Japanese, 2010年ハイパフォーマンスコンピューティングと計算科学シンポジウム (HPCS2010), 情報処理学会, 東京
Jan. 2010

実生活における高齢者向けポータブル生活支援システムの評価-運動強度と日常行動との関連-
矢崎俊志; 松永俊雄
Oral presentation, Japanese, 計測自動制御学会システムインテグレーション部門講演会(SI2009),計測自動制御学会システムインテグレーション部門講演会(SI2009)
Dec. 2009

学生のプロファイルと希望進路および履修登録に基づく情報掲示システム
寺澤賢人; 矢崎俊志; 月江伸弘; 松永俊雄; 中村太一
Oral presentation, Japanese, 平成21年電気学会産業応用部門大会予稿集,平成21年電気学会産業応用部門大会
Sep. 2009

2次元メッシュネットワーク上での全対体通信アルゴリズム性能比較
高上治之; 鈴木悠太郎; 矢崎俊志; 石畑宏明
Oral presentation, Japanese, 第8回情報科学技術フォーラム (FIT2009),第8回情報科学技術フォーラム (FIT2009)
Sep. 2009

メッセージフローに基づく通信ネットワークシミュレータとその並列化
鈴木悠太郎; 高上治之; 矢崎俊志; 石畑宏明
Oral presentation, Japanese, 第8回情報科学技術フォーラム (FIT2009),第8回情報科学技術フォーラム (FIT2009)
Sep. 2009

RFID と生体センシング技術を利用した高齢者向け快適生活支援システム
矢崎俊志; 月江伸弘; 松永俊雄
Oral presentation, Japanese, 電気学会研究会資料 (産業システム情報化研究会),産業システム情報化研究会
Mar. 2009

携帯電話における電子透かしアルゴリズムの実装と評価
小関洋助; 矢崎俊志; 松永俊雄; 月江伸弘
Oral presentation, Japanese, 情報処理学会 第71回全国大会 講演予稿集,情報処理学会 第71回全国大会
Mar. 2009

機能選択を補助するユーザ適応型インターフェースの開発と評価
月江伸弘; 森藤央一郎; 矢崎俊志; 松永俊雄
Oral presentation, Japanese, 情報処理学会 第71回全国大会 講演予稿集,情報処理学会 第71回全国大会
Mar. 2009

ユーザ適応型インタフェースを持つ携帯電話端末の開発
月江伸弘; 森藤央一郎; 矢崎俊志; 松永俊雄
Oral presentation, Japanese, 計測自動制御学会システムインテグレーション部門講演会(SI2008),計測自動制御学会システムインテグレーション部門講演会(SI2008)
Dec. 2008

娯楽機能を有する異変検知システムの提案
矢崎俊志; 月江伸弘; 松永俊雄
Oral presentation, Japanese, 計測自動制御学会システムインテグレーション部門講演会(SI2008),計測自動制御学会システムインテグレーション部門講演会(SI2008)
Dec. 2008

ウェアラブル生体センサを用いた高齢者向け異変検知システムの提案
矢崎俊志; 松永俊雄
Oral presentation, Japanese, 計測自動制御学会システムインテグレーション部門講演会(SI2007),計測自動制御学会システムインテグレーション部門講演会(SI2007)
Dec. 2007

車載単眼カメラの動画像による衝突危険予測
渡邊元気; 矢崎俊志; 松永俊雄
Oral presentation, Japanese, 第70回情報処理学会全国大会講演論文集,第70回情報処理学会全国大会
2007

FFT乗算器の最適化実装
矢崎俊志; 阿部公輝
Oral presentation, Japanese, 電子情報通信学会技術報告(VLSI 設計技術研究会),VLSI設計技術研究会
Dec. 2004

高速Fourier 変換を用いた多倍長乗算器の設計と評価およびVLSI への実装
矢崎俊志; 阿部公輝
Oral presentation, Japanese, 電子情報通信学会技術報告(VLSI設計技術研究会),VLSI設計技術研究会
Nov. 2003

高速Fourier変換を用いた多倍長乗算器の構成法とハードウェア実装法の検討
矢崎俊志; 阿部公輝
Oral presentation, Japanese, 情報処理学会 第65回全国大会 講演予稿集,情報処理学会 第65回全国大会
Mar. 2003

多倍長機能を持ったプロセッサの実現方法の検討-乗算器の実装-
月江伸弘; 矢崎俊志; 松永俊雄
Oral presentation, Japanese, 電子情報通信学会総合大会講演論文集
Mar. 2002

ACM

電子情報通信学会

情報処理学会

IEEE

「Living Town」
長谷 海平; 矢崎 俊志
10 Jul. 2020

計算アクセラレータによる高効率なネットワークサービス基盤の実現
Syunji Yazaki
Principal investigator, GPU および Co-Processor ボードを用いて,L3 以上のネットワークレイヤを実装する HTTP 等のサービスプログラムについて,処理の特徴を考慮した高速化を行う.汎用の Co-Processor ボードを用いて,多数のプロセスにより,リクエストを効率よく並列処理する手法を提案する.マッチ ングや暗号化などの計算バウンドな処理に対しては GPU による既存の高速化手法を適用する.提案 手法でサービスを構築し,実際の基幹ネットワーク上で評価を行う.本研究により,安価な PC サーバで,コスト性能比の高いネットワーク基盤の実現が見込まれる.これは既存の情報基盤の高効率化, 新サービス構築の低コスト化につながり,有用なサービス開発を加速させる効果も期待できる.
01 Apr. 2014 - 31 Mar. 2018