SOWA MASAHIRO

Emeritus Professor etc.Emeritus Professor
  • Profile:
    1. Electronics circuit

    2. LSI circuit

    3. Telephone exchanger

    4. Parallel computer system

    5. Parallel computer Language

    6. Parallel computer operating system

    7. Parallel computer architecture

    8. Compiler for parallel processor

    9. Computer network in case of natural disaster
Researcher Information

Degree

  • Docter of Engineering, Nagoya University

Research Keyword

  • Ad hoc network
  • Parallelized compiler
  • Parallel computer systems
  • Parallel processing
  • Parallel computer architecture
  • アドフォックネットワーック
  • 並列化コンパイラ
  • コンピュータシステム
  • 並列処理
  • 計算機アーキテクチャ

Educational Background

  • Mar. 1974
    Nagoya University, Graduate School, Division of Engineering, 電気及電子工学専攻
Research Activity Information

Paper

  • Efficient compilation for queue size constrained queue processors
    Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
    PARALLEL COMPUTING, 35, 4, 213-225, Apr. 2009
    Scientific journal, English
    DOI URL
  • A new code generation algorithm for 2-offset producer order queue computation model
    Arquirnedes Canedo; Ben Abderazek; Masahiro Sowa
    COMPUTER LANGUAGES SYSTEMS & STRUCTURES, 34, 4, 184-194, Dec. 2008, Peer-reviwed
    Scientific journal, English
    DOI URL
  • Queue Programs Characterization using Performance Bounds
    Arquimedes Canedo; Masahiro Sowa
    International Workshop on Modern Science and Technology 2008, -, -, -, Nov. 2008
    International conference proceedings, English
  • Construction of a SSA-based Queue Compiler
    Yuki Nakanishi; Masahiro Sowa; Arquimedes Canedo
    International Workshop on Modern Science and Technology 2008(IWMST2008), -, -, -, Nov. 2008
    International conference proceedings, English
  • The QC-2 parallel Queue processor architecture
    Ben A. Abderazek; Arquimedes Canedo; Tsutomu Yoshinaga; Masahiro Sowa
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 68, 2, 235-245, Feb. 2008, Peer-reviwed
    Scientific journal, English
    DOI URL
  • Queue Processor as Next Generation Fundamental ICT Infrastructure
    Masahiro Sowa; Arquimedes Canedo
    Kantaoui Forum TJASSST 2008, --, --, --, 2008, Peer-reviwed
    International conference proceedings, English
  • Natural Instruction Level Parallelism-aware Compiler for High-Performance Embedded QueueCore
    Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    Journal of Embedded Computing, ==, ==, 2008, Peer-reviwed
    Scientific journal, English
  • Compiling for Reduced Bit-Width Queue Processors
    Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
    Journal of Signal Processing Systems, 1939-8018, 2008, Peer-reviwed
    Scientific journal, English
  • Quantitative evaluation of common subexpression elimination on queue machines
    Arquimedes Canedo; Masahiro Sowa; Ben A. Abderazek
    Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN, 25-30, 2008, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • Mathematical model for multiobjective synthesis of NoC architectures
    Ben A. Abderazek; Mushfiquzzaman Akanda; Tsutomu Yoshinaga; Masahiro Sowa
    Proceedings of the International Conference on Parallel Processing Workshops, 1, 36-41, 2007, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • Compiler Framework for an Embedded 32-bit Queue Processo
    Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    2007 International Conference on Convergence Information Technology (ICCIT¨07), 1793-1796, 2007, Peer-reviwed
    International conference proceedings, English
  • Dual-Execution Mode Processor Architecture for embedded applications
    Md. Musfiquzzaman Akanda; Ben Abderazek; Masahiro Sowa
    Journal of Mobile Multimedia, 13, 4, 347-370, 2007, Peer-reviwed
    Scientific journal, English
  • New code generation algorithm for QueueCore - An embedded processor with high ILP
    Arquirnedes Canedo; Ben A. Abderazek; Masahiro Sowa
    EIGHTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS, 185-192, 2007, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • Queue register file optimization algorithm for QueueCore processor
    Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS, 169-176, 2007, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • Novel addressing method for aggregate types in queue processors
    Teruhisa Yuki; Arquimedes Canedo; Ben A. Abderazek; Masahiro Sowa
    2007 International Conference on Convergence Information Technology, ICCIT 2007, 1793-1796, 2007, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model
    Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    The 2007 IFIP International Conference on Embedded and Ubiquitous Computing EUC2007, 197-208, 2007, Peer-reviwed
    International conference proceedings, English
  • Compiler Support for Code Size Reduction using a Queue-based Processo
    Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    Transactions on High-Performance Embedded Architectures and Compilers, 2, 3, 153-169, 2007, Peer-reviwed
    Scientific journal, English
  • Optimizing Reaching Definitions Overhead in Queue Processors
    Yuuki Nakanisi; Arquimedes Canedo; Ben Abderazek; Masahiro Sowa
    Journal of Convergence Information technology, 2, 4, 36-40, 2007
    Scientific journal, English
  • On the Design of a Dual-Execution Mode Processor: Architecture and Preliminary Evaluation
    M. Akanda; B. A. Abderazek; M.Sowa
    ISPA-2006 International Symposium on Parallel and Distributed Processing and Applications, 37-46, Dec. 2006, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • High-level modeling and FPGA prototyping of produced order parallel queue processor core
    Ben A. Abderazek; Tsutomu Yoshinaga; Masahiro Sowa
    JOURNAL OF SUPERCOMPUTING, 38, 1, 3-15, Oct. 2006, Peer-reviwed
    Scientific journal, English
    DOI URL
  • Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC
    B. A. Abderazek; S. Kawata; T. Yoshinaga; M. Sowa
    the 3rd Int. Workshop on Embedded Computing The 35th Int. Conf. on Parallel Processing, ICPP, pp217-229, Aug. 2006, Peer-reviwed
    Scientific journal, English
  • Consumed-Order Queue Computation Model-New Model to Solve Drawbacks of Queue Computation Model-
    Masahiro Sowa; Halcham Kutluk; B. A. Abderazek; Sotaro Kawata
    The International Workshop on Modern Science and Technology 2006, 4, 1, 353-357, May 2006
    International conference proceedings, English
  • A GCC-based Compiler for the Queue Register Processor (QRP-GCC)
    Arquimedes Canedo; B. A. Abderazek; M.Sowa
    The International Workshop on Modern Science and Technology 2006, 250-255, 2006, Peer-reviwed
    International conference proceedings, English
  • Design and Architecture for an Embedded 32-bit QueueCore
    B. A. Abderazek; S. Kawata; M. Sowa
    the International Journal of Embedded Computing, Special issue on Single-Chip Multi-core Architectures and related research, 2, 2, pp. 191-205, 2006
    Scientific journal, English
  • Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation
    A. Markovskij; B. Abderazek; S. Kawata; M. Sowa
    the 38th International Symposium on Microarchitecture, (MICRO-38,MSP7), 29-35, Dec. 2005, Peer-reviwed
    International conference proceedings, English
  • Parallel queue processor architecture based on produced order computation model
    M Sowa; BA Abderazek; T Yoshinaga
    JOURNAL OF SUPERCOMPUTING, 32, 3, 217-229, Jun. 2005, Peer-reviwed
    Scientific journal, English
    DOI URL
  • An efficient dynamic switching mechanism (DSM) for hybrid processor architecture
    AM Musfiquzzaman; BA Abderazek; S Kawata; M Sowa
    EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, 3824, 77-86, 2005, Peer-reviwed
    Scientific journal, English
  • Modular design structure and high-level prototyping for novel embedded processor core
    BA Abderazek; S Kawata; T Yoshinaga; M Sowa
    EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, 3824, 340-349, 2005
    Scientific journal, English
    DOI URL
  • Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters
    V. Ta Qo; T. Yoshinaga; B. A. Abderazek; M. Sowa
    IPSJ Transactions on Advanced Computing Systems, Information Processing Society of Japan (IPSJ), 46, SIG3(ACS8), 25-37, 2005, This paper proposes a middle-grain approach to construct hybrid MPI-OpenMP solutions for SMP clusters from an existing MPI algorithm. Experiments on different cluster platforms show that our solutions exceed the solutions that are based on the de-facto MPI model in most cases, and occasionally by as much as 40% of performance. We also prove an automatic outperformance of a thread-to-thread communication model over a traditional process-to-process communication model in hybrid solutions. In addition, the paper performs a detailed analysis on the hardware and software factors affecting the performance of MPI in comparison to hybrid models.
    Scientific journal, English
    URL
    URL 2
  • Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme,
    Ben Abderazek; Arsenji Markovski; Soichi Shigeta; Tsutom Yoshinaga; Masahiro Sowa
    The 7th Perfomance Computaing and Grid in Asia Pacific Reagion(HPCAsia2004), Jul. 2004, Peer-reviwed
    International conference proceedings, English
    DOI URL
  • QJava:Inregrate Queue Computaional Model into Java
    Soichi Shigeta; Li-Qiang Wang; N.Yagishita; Ben Abderazek; Tsutomu Yoshinaga; Masahiro Sowa
    Proceedings of The Joint Japan-Tunisia worrkshop on ComputerSystem and Information Technology(JT-CSIT'04, pp60-65, 2004, Peer-reviwed
    International conference proceedings, English
  • Queru Machine with Queue Extention Mechanism
    Sotaro Kawata; Masahiro Sowa
    COOL Chips Ⅶ, 2004, Peer-reviwed
    International conference proceedings
  • On the design of a register queue based processor architecture (FaRM-rq)
    BA Abderazek; S Shigeta; T Yoshinaga; M Sowa
    PARALLEL AND DISTRIBUTED PROCESSING AND APPLICATIONS, PROCEEDINGS, 2745, 248-262, 2003, Peer-reviwed
    Scientific journal, English
  • QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java
    L. Wang; B. A. Abderazek; S. Shigeta; T. Yoshinaga; M. Sowa
    Proceedings of International Technical Conference in Circuits/Systems, Computers and Communications, 900-903, 2003, Peer-reviwed
    International conference proceedings, English
  • Proposal and Design of a Parallel Queue Processor Architecture(PQP)
    Masahiro Sowa; Ben A. Abderazek; Soichi Shigeta; Tsutomu Yoshinaga
    Proceedings of the 14th IASTED International Conference Parallel and Distributed Computing and Systems, 554-560, Nov. 2002, Peer-reviwed
    International conference proceedings, English
  • "FARM Queue Mode: On a Practical Queue Execution Model(QEM)"
    Ben,A.,Abderrazek; Kirilka Nikolova; Tutomu Yoshinaga; Masahiro Sowa
    TIWSS'2001, Oct. 2001, Peer-reviwed
    International conference proceedings, English
  • "Dynamic Crirical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing System"
    Kirilka Nikolova; Ben Abderazek; Masahiro Sowa
    ITC-CSCC'2001, 2, Jul. 2001, Peer-reviwed
    International conference proceedings, English
  • "Access Route Control by Extended Key/Lock Scheme"
    Shigeta,S; Shimizu,K; Sowa,M
    International Journal of Computer Systems, Science and Engineering,CRL Publishing Ltd., 2001, Peer-reviwed
    International conference proceedings, English
  • "Proposition and Evaluation of Parallelism-Independent Scheduling Algorithm for DAGs of Tasks with Non-Uniform Execution Times"
    Kirilka Vassileva Nikolova; Atsusi Maeda; Masahiro Sowa
    IEICE Transactions, E48-A, 6, 2001, Peer-reviwed
    Scientific journal, English
  • "キー/ロック式の拡張によるアクセスルートコントロール"
    繁田 聡一; 清水 謙多郎; 曽和 将容
    情報処理学会論文誌, 42, 6, 2001, Peer-reviwed
    Japanese
  • 浅い束縛によるスコープ変数が存在する時の末尾再呼び出し
    前田敦司; 曽和将容
    情報処理学会論文誌, 40, 3, 2000, Peer-reviwed
    Japanese
  • DRA: Dynamic Register Allocation for Accurate Parallel Instruction Issue and Dispatch in FARM Microprocessor
    Ben Abdallah Abderrazek; Masahiro Sowa
    The Third International Workshop on Advanced Parallel Processing Technologies APPT'99, October 19-21, Oct. 1999, Peer-reviwed
    International conference proceedings, English
  • Design of a superscalar Processor Based on Queue Machine Computation Model
    Shusuke Okamoto; Hitoshi Suzuki; Atusi Maeda; Masahiro Sowa
    1999 IEEE Pacific Rim Conferences, Computers and Signal Processing（PACRIM 1999），August 22-24, Aug. 1999
    International conference proceedings, English
  • A survey on the advances of diskI/O performance Metrics
    Ben Abdallah Abderrazek; Mudar Sarem; Masahiro Sowa
    International Conference on Robotics,Vision and Parallel Processing for Automation, Jul. 1999
    International conference proceedings, English
  • Parallelism-Free Scheduling Method
    Kirilka Nikolova; Atusi Maeda; Masahiro Sowa
    ITC-CSCC'99（International Technical Conference on Circuits/Systems, Computers and Communications）, Jun. 1999
    International conference proceedings, English
  • A Flexible Access Control Mechanism Based on the Key/Lock Scheme
    Souichi Shigeta; Kenichi Shimizu; Shusuke Okamoto; Masahiro Sowa
    ITC-CSCC'99（International Technical Conference on Circuits/Systems, Computers and Communications）, Jun. 1999
    International conference proceedings, English
  • Relational Database Operations on Multi-processor with Program Controlled Cache Level Memory
    Mitsuaki Nakasumi; Shusuke Okamoto; Masahiro Sowa
    PDPTA'99 Conference , LasVegas, June28-July1, 1999
    International conference proceedings, English

Books and other publications

  • 情報リテラシイ
    立花康夫; 曽和将容; 春日秀雄
    Japanese, Joint work, コロナ社, 2008
  • コンピュータアーキテクチャ
    曽和将容
    Japanese, Editor, コロナ社, 2006
  • コンピュータアーキテクチャ原理
    曽和将容
    Japanese, Editor, コロナ社, 1993
  • コンピュータ基礎工学
    曽和将容; 柳瀬龍郎; 今井正治; 丹羽敏之
    Japanese, Joint work, 昭晃堂, 1992
  • 並列ＰＲＯＬＯＧコンピュータ
    曽和将容
    Japanese, Editor, 啓学出版, 1989
  • デ－タフロ－マシンと言語
    曽和将容
    Japanese, Editor, 昭晃堂, 1986
  • マイクロコンピュ－タＭＣ６８０９の考え方
    曽和将容
    Japanese, Editor, オ－ム社, 1982
  • トランジスタ回路を学ぶ人のために
    曽和将容
    Japanese, Joint work, オーム社, 1979
  • ディジタル回路の考え方
    曽和将容; 清水賢資
    Japanese, Joint work, オ－ム社, 1979

Affiliated academic society

  • IEEE
  • ACM
  • 情報処理学会
  • 電子情報通信学会
  • 日本ソフトウェア科学会

Industrial Property Rights

  • キュープロセッサおよびキュープロセッサによるデータ処理方法、およびキュープロセッサによるデータ処理プログラム
    Patent right, 特願2007-40857, Date applied: 21 Feb. 2007
  • マルチディメンジョナルキュープロセッサ
    Patent right, 特願2006-037033, Date applied: 14 Feb. 2006
  • 並列キュープロセッサの高速実行可能命令の判別方法及びその回路
    Patent right, 特願2001-19933, Date applied: 29 Jan. 2002, 特許第3712674, Date issued: 26 Aug. 2005
  • キュープロセッサにおける投機実行方法
    Patent right, 曽和将容, 特願2002-019934, Date applied: 20 Jan. 2002, 曽和将容 科学技術振興事業団, 特許第3712675号, Date issued: 26 Aug. 2005
  • キュープロセッサ
    Patent right, 特願2001-158869, Date applied: 28 May 2001, 特許第3701583号, Date issued: 25 Jul. 2005
  • キューVLIWプロセッサ
    Patent right, 特願2001-208239, Date applied: 09 Jul. 2001, 特許第3696531号, Date issued: 08 Jul. 2005
  • ファンクション・オペランド分割プロセッサ
    Patent right, 特願2001-208240, Date applied: 09 Jul. 2001, 特許第3634292, Date issued: 07 Jan. 2005
  • キューを主に中間格納用メモリとして使うキュープロセッサ
    Patent right, 曽和将容, 特願2004-105469, Date applied: 31 Mar. 2004, 曽和将容 科学技術振興事業団
  • キュープロセッサにおける投機実行方法
    Patent right, 特願2002-019934, Date applied: 29 Jan. 2002, 特許第3712675号, Date issued: 29 Jan. 2003
  • キュー仮想マシン
    Patent right, 特願2001-208241, Date applied: 09 Jul. 2001
  • プログラマブル･コントローラ
    Patent right, -, 第1668294, Date issued: Nov. 1983
  • コントロールフロー並列計算機方式
    Patent right, 特願昭58-20863, Date applied: 1983